/*
* Print the CPU specific information
*/
int print_cpuinfo(void)
{
char buf[4][32];
printf("CPU : %s\n", "STM32F103ZET (Cortex-M3)");
strmhz(buf[0], clock_get(CLOCK_SYSCLK));
strmhz(buf[1], clock_get(CLOCK_HCLK));
strmhz(buf[2], clock_get(CLOCK_PCLK1));
strmhz(buf[3], clock_get(CLOCK_PCLK2));
printf("Freqs: SYSCLK=%sMHz,HCLK=%sMHz,PCLK1=%sMHz,PCLK2=%sMHz\n",
buf[0], buf[1], buf[2], buf[3]);
return 0;
}
/* delay x useconds */
void __udelay(ulong usec)
{
#if 0
ulong clc, tmp;
volatile struct cm3_systick *systick =
(volatile struct cm3_systick *)(CM3_SYSTICK_BASE);
clc = usec * (clock_get(CLOCK_SYSTICK) / 1000000);
/*
* Get current timestamp
*/
tmp = systick->val;
/*
* Loop till event
*
* The SYSTICK timer count downwards.
*/
if (tmp < clc) {
while (systick->val < tmp ||
systick->val > (CM3_SYSTICK_LOAD_RELOAD_MSK - 1 -
clc + tmp)) ; /* nop */
} else {
while (systick->val > (tmp - clc) && systick->val <= tmp) ;
}
#else
ulong tmp = usec/1000;
HAL_Delay(tmp ? tmp : 1);
#endif
}
/*
* Print the CPU specific information
*/
int print_cpuinfo(void)
{
char buf[5][32];
printf("CPU : %s\n", "SmartFusion FPGA (Cortex-M3 Hard IP)");
strmhz(buf[0], clock_get(CLOCK_FCLK));
strmhz(buf[1], clock_get(CLOCK_PCLK0));
strmhz(buf[2], clock_get(CLOCK_PCLK1));
strmhz(buf[3], clock_get(CLOCK_ACE));
strmhz(buf[4], clock_get(CLOCK_FPGA));
printf("Freqs: FCLK=%sMHz,PCLK0=%sMHz,PCLK1=%sMHz,ACE=%sMHz,"
"FPGA=%sMHz\n",
buf[0], buf[1], buf[2], buf[3], buf[4]);
return 0;
}
/*
* Print the CPU specific information
*/
int print_cpuinfo(void)
{
char buf[2][32];
#if defined(CONFIG_SYS_ARMCORTEXM4)
printf("CPU : %s\n", "LPC43xx series (Cortex-M4/M0)");
#else
printf("CPU : %s\n", "LPC18xx series (Cortex-M3)");
#endif
strmhz(buf[0], clock_get(CLOCK_SYSTICK));
strmhz(buf[1], clock_get(CLOCK_CCLK));
printf("Freqs: SYSTICK=%sMHz,CCLK=%sMHz\n",
buf[0], buf[1]);
return 0;
}
static inline void disp_clock(){
struct clockval cval;
clock_get(&cval);
struct timeval tval;
time_get(&tval);
sprintf_P(lcd_buf_l1, PSTR("Clock %02u:%02u:%02u"), cval.h, cval.m, cval.s);
sprintf_P(lcd_buf_l2, PSTR("Time %02u:%02u:%02u"), tval.h, tval.m, tval.s);
lcd_write_buffer(lcd_buf_l1, lcd_buf_l2);
}
int timer_init(void)
{
struct stm32_tim2_5 *tim = (struct stm32_tim2_5 *)STM32_TIM2_BASE;
setbits_le32(&STM32_RCC->apb1enr, RCC_APB1ENR_TIM2EN);
if (clock_get(CLOCK_AHB) == clock_get(CLOCK_APB1))
writel((clock_get(CLOCK_APB1) / CONFIG_SYS_HZ_CLOCK) - 1,
&tim->psc);
else
writel(((clock_get(CLOCK_APB1) * 2) / CONFIG_SYS_HZ_CLOCK) - 1,
&tim->psc);
writel(0xFFFFFFFF, &tim->arr);
writel(TIM_CR1_CEN, &tim->cr1);
setbits_le32(&tim->egr, TIM_EGR_UG);
gd->arch.tbl = 0;
gd->arch.tbu = 0;
gd->arch.lastinc = 0;
return 0;
}
ulong get_timer(ulong base)
{
#if 0
volatile struct cm3_systick *systick =
(volatile struct cm3_systick *)CM3_SYSTICK_BASE;
ulong now = systick->val;
if (lastdec >= now)
timestamp += lastdec - now;
else
timestamp += lastdec + CM3_SYSTICK_LOAD_RELOAD_MSK - 1 - now;
lastdec = now;
return timestamp / (clock_get(CLOCK_SYSTICK) / CONFIG_SYS_HZ) - base;
#else
lastdec = HAL_GetTick();
return HAL_GetTick() - base;
#endif
}
void pwm_init(){
long pclk;
int pwm_div;
pclk = clock_get(CLOCK_PCLK);
pwm_div = pclk/PWM_CLK - 1;
lpc178x_periph_enable(LPC178X_SCC_PCONP_PWM1_MSK, 1);
LPC178X_PWM1->pwm_ir = 0x73f; //clear all pending
LPC178X_PWM1->pwm_tcr = 0x0;
LPC178X_PWM1->pwm_ctcr = 0x0;
LPC178X_PWM1->pwm_mcr = 0x0;
LPC178X_PWM1->pwm_ccr = 0x0;
LPC178X_PWM1->pwm_pcr = 0x0;
LPC178X_PWM1->pwm_ler = 0x0;
LPC178X_PWM1->pwm_pr = pwm_div;
LPC178X_PWM1->pwm_mr0 = PWM_TOTCNT;
LPC178X_PWM1->pwm_ler |= 0x1<<0; //update mr0
//LPC178X_PWM1->pwm_tcr |= 0x1<<1; //pwm counter reset
//LPC178X_PWM1->pwm_tcr &= 0x9; //
LPC178X_PWM1->pwm_mr1 = PWM_LOWCNT_START;
LPC178X_PWM1->pwm_ler |= 0x1<<1; //update mr1
//LPC178X_PWM1->pwm_tcr |= 0x1<<1; //pwm counter reset
//LPC178X_PWM1->pwm_tcr &= 0x9; //
LPC178X_PWM1->pwm_mcr = 0x1<<1; //PWMTC reset when PWMTC == PWMMR0
LPC178X_PWM1->pwm_pcr |= 0x1<<9; //pwm1[1] output enable
LPC178X_PWM1->pwm_tcr |= 0x1<<1; //pwm counter reset
LPC178X_PWM1->pwm_tcr &= 0x9; //
LPC178X_PWM1->pwm_tcr |= 0x1<<0; //pwm counter enable
LPC178X_PWM1->pwm_tcr |= 0x1<<3; //pwm enable
}
void board_video_init(GraphicDevice *pGD){
long pclk;
int lcd_div;
unsigned int *pboost;
unsigned int *pconp;
lpc178x_periph_enable(LPC178X_SCC_PCONP_LCD_MSK, 1);
pboost = (unsigned int *)0x400FC1B0;
pconp= (unsigned int *)0x400FC0C4;
printf("pboost = 0x%x\n", *pboost);
printf("pconp = 0x%x\n", *pconp);
pclk = clock_get(CLOCK_SYSTICK);
lcd_div = pclk / (pGD->modeIdent[0] * 1000000);
printf("lcd_div = %d\n", lcd_div);
GLCD_Ctrl(0);
LPC178X_LCD->crsr_ctrl &= ~(0x1<<0); //不使用光标
LPC178X_LCD->lcd_ctrl = 0x0;
LPC178X_LCD->lcd_ctrl |= (0x6<<1); //16bpp, 5:6:5 mode
LPC178X_LCD->lcd_ctrl |= (0x1<<5); // TFT panel
LPC178X_LCD->lcd_ctrl &= ~(0x1<<7); // single panel
LPC178X_LCD->lcd_ctrl &= ~(0x1<<8); // RGB normal sequence
LPC178X_LCD->lcd_ctrl &= ~(0x1<<9); // little order
LPC178X_LCD->lcd_ctrl &= ~(0x1<<10); // little order in one byte
LPC178X_LCD->lcd_ctrl &= ~(0x1<<11); // disable LCD_VD[0:23]
if(lcd_div > 0)
lcd_div -= 1;
else
lcd_div = 0;
LPC178X_SCC->lcd_cfg = lcd_div;
LPC178X_LCD->lcd_pol |= (1<<26); // bypass inrenal clk divider
LPC178X_LCD->lcd_pol &= ~(1<<5); // clock source for LCD is CCLK
LPC178X_LCD->lcd_pol |= (1<<11); // LCDFP pin is active Low and inactive HIGH
LPC178X_LCD->lcd_pol |= (1<<12); // LCDLP pin is active Low and inactive HIGH
LPC178X_LCD->lcd_pol |= (1<<13); // data is driven out into the LCD on the falling edge
//active high
LPC178X_LCD->lcd_pol &= ~(1<<14); // LCD_ENAB_M is active high
LPC178X_LCD->lcd_pol &= ~(0x3ff<<16);
LPC178X_LCD->lcd_pol |= ((pGD->winSizeX)-1)<<16; //pixel per line
// init Horizontal Timing
LPC178X_LCD->lcd_timh = 0;
LPC178X_LCD->lcd_timh |= ((pGD->modeIdent[1]) - 1)<<24;
LPC178X_LCD->lcd_timh |= ((pGD->modeIdent[2]) - 1)<<16;
LPC178X_LCD->lcd_timh |= ((pGD->modeIdent[5]) - 1)<<8;
LPC178X_LCD->lcd_timh |= ((pGD->winSizeX)/16 - 1)<<2;
// init Vertical Timing
LPC178X_LCD->lcd_timv = 0;
LPC178X_LCD->lcd_timv |= (pGD->modeIdent[3])<<24;
LPC178X_LCD->lcd_timv |= (pGD->modeIdent[4])<<16;
LPC178X_LCD->lcd_timv |= ((pGD->modeIdent[6]) - 1)<<10;
LPC178X_LCD->lcd_timv |= (pGD->winSizeY) - 1;
// init lcd base addr
LPC178X_LCD->lcd_upbase = pGD->frameAdrs;
LPC178X_LCD->lcd_lpbase = pGD->frameAdrs;
GLCD_Ctrl(1);
pwm_init();
}
int dram_init(void)
{
u32 freq;
int rv;
rv = fmc_setup_gpio();
if (rv)
return rv;
setbits_le32(&STM32_RCC->ahb3enr, STM32_RCC_ENR_FMC);
/*
* Get frequency for NS2CLK calculation.
*/
freq = clock_get(CLOCK_AHB) / CONFIG_SYS_RAM_FREQ_DIV;
writel(CONFIG_SYS_RAM_FREQ_DIV << FMC_SDCR_SDCLK_SHIFT
| SDRAM_RPIPE << FMC_SDCR_RPIPE_SHIFT
| SDRAM_RBURST << FMC_SDCR_RBURST_SHIFT,
&STM32_SDRAM_FMC->sdcr1);
writel(CONFIG_SYS_RAM_FREQ_DIV << FMC_SDCR_SDCLK_SHIFT
| SDRAM_CAS << FMC_SDCR_CAS_SHIFT
| SDRAM_NB << FMC_SDCR_NB_SHIFT
| SDRAM_MWID << FMC_SDCR_MWID_SHIFT
| SDRAM_NR << FMC_SDCR_NR_SHIFT
| SDRAM_NC << FMC_SDCR_NC_SHIFT
| SDRAM_RPIPE << FMC_SDCR_RPIPE_SHIFT
| SDRAM_RBURST << FMC_SDCR_RBURST_SHIFT,
&STM32_SDRAM_FMC->sdcr2);
writel(SDRAM_TRP << FMC_SDTR_TRP_SHIFT
| SDRAM_TRC << FMC_SDTR_TRC_SHIFT,
&STM32_SDRAM_FMC->sdtr1);
writel(SDRAM_TRCD << FMC_SDTR_TRCD_SHIFT
| SDRAM_TRP << FMC_SDTR_TRP_SHIFT
| SDRAM_TWR << FMC_SDTR_TWR_SHIFT
| SDRAM_TRC << FMC_SDTR_TRC_SHIFT
| SDRAM_TRAS << FMC_SDTR_TRAS_SHIFT
| SDRAM_TXSR << FMC_SDTR_TXSR_SHIFT
| SDRAM_TMRD << FMC_SDTR_TMRD_SHIFT,
&STM32_SDRAM_FMC->sdtr2);
writel(FMC_SDCMR_BANK_2 | FMC_SDCMR_MODE_START_CLOCK,
&STM32_SDRAM_FMC->sdcmr);
udelay(200); /* 200 us delay, page 10, "Power-Up" */
FMC_BUSY_WAIT();
writel(FMC_SDCMR_BANK_2 | FMC_SDCMR_MODE_PRECHARGE,
&STM32_SDRAM_FMC->sdcmr);
udelay(100);
FMC_BUSY_WAIT();
writel((FMC_SDCMR_BANK_2 | FMC_SDCMR_MODE_AUTOREFRESH
| 7 << FMC_SDCMR_NRFS_SHIFT), &STM32_SDRAM_FMC->sdcmr);
udelay(100);
FMC_BUSY_WAIT();
writel(FMC_SDCMR_BANK_2 | (SDRAM_MODE_BL << SDRAM_MODE_BL_SHIFT
| SDRAM_MODE_CAS << SDRAM_MODE_CAS_SHIFT)
<< FMC_SDCMR_MODE_REGISTER_SHIFT | FMC_SDCMR_MODE_WRITE_MODE,
&STM32_SDRAM_FMC->sdcmr);
udelay(100);
FMC_BUSY_WAIT();
writel(FMC_SDCMR_BANK_2 | FMC_SDCMR_MODE_NORMAL,
&STM32_SDRAM_FMC->sdcmr);
FMC_BUSY_WAIT();
/* Refresh timer */
writel(SDRAM_TREF, &STM32_SDRAM_FMC->sdrtr);
/*
* Fill in global info with description of SRAM configuration
*/
gd->bd->bi_dram[0].start = CONFIG_SYS_RAM_BASE;
gd->bd->bi_dram[0].size = CONFIG_SYS_RAM_SIZE;
gd->ram_size = CONFIG_SYS_RAM_SIZE;
return rv;
}
/*
* This function is derived from PowerPC code (timebase clock frequency).
* On ARM it returns the number of timer ticks per second.
*/
ulong get_tbclk(void)
{
return clock_get(CLOCK_SYSTICK);
}
int dram_init(void)
{
u32 freq;
int rv;
/*
* Enable FMC interface clock
*/
STM32_RCC->ahb3enr |= STM32_RCC_ENR_FMC;
/*
* Get frequency for NS2CLK calculation.
*/
freq = clock_get(CLOCK_HCLK) / CONFIG_SYS_RAM_FREQ_DIV;
STM32_SDRAM_FMC->sdcr1 = (
CONFIG_SYS_RAM_FREQ_DIV << FMC_SDCR_SDCLK_SHIFT |
SDRAM_CAS << FMC_SDCR_CAS_SHIFT |
SDRAM_NB << FMC_SDCR_NB_SHIFT |
SDRAM_MWID << FMC_SDCR_MWID_SHIFT |
SDRAM_NR << FMC_SDCR_NR_SHIFT |
SDRAM_NC << FMC_SDCR_NC_SHIFT |
0 << FMC_SDCR_RPIPE_SHIFT |
1 << FMC_SDCR_RBURST_SHIFT
);
STM32_SDRAM_FMC->sdtr1 = (
SDRAM_TRCD << FMC_SDTR_TRCD_SHIFT |
SDRAM_TRP << FMC_SDTR_TRP_SHIFT |
SDRAM_TWR << FMC_SDTR_TWR_SHIFT |
SDRAM_TRC << FMC_SDTR_TRC_SHIFT |
SDRAM_TRAS << FMC_SDTR_TRAS_SHIFT |
SDRAM_TXSR << FMC_SDTR_TXSR_SHIFT |
SDRAM_TMRD << FMC_SDTR_TMRD_SHIFT
);
STM32_SDRAM_FMC->sdcmr = FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_START_CLOCK;
udelay(200); /* 200 us delay, page 10, "Power-Up" */
FMC_BUSY_WAIT();
STM32_SDRAM_FMC->sdcmr = FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_PRECHARGE;
udelay(100);
FMC_BUSY_WAIT();
STM32_SDRAM_FMC->sdcmr = (
FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_AUTOREFRESH |
7 << FMC_SDCMR_NRFS_SHIFT
);
udelay(100);
FMC_BUSY_WAIT();
#define SDRAM_MODE_BL_SHIFT 0
#define SDRAM_MODE_CAS_SHIFT 4
#define SDRAM_MODE_BL 0
#define SDRAM_MODE_CAS SDRAM_CAS
STM32_SDRAM_FMC->sdcmr = FMC_SDCMR_BANK_1 |
(
SDRAM_MODE_BL << SDRAM_MODE_BL_SHIFT |
SDRAM_MODE_CAS << SDRAM_MODE_CAS_SHIFT
) << FMC_SDCMR_MODE_REGISTER_SHIFT | FMC_SDCMR_MODE_WRITE_MODE;
udelay(100);
FMC_BUSY_WAIT();
STM32_SDRAM_FMC->sdcmr = FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_NORMAL;
FMC_BUSY_WAIT();
/* Refresh timer */
STM32_SDRAM_FMC->sdrtr = SDRAM_TREF;
/*
* Fill in global info with description of SRAM configuration
*/
gd->bd->bi_dram[0].start = CONFIG_SYS_RAM_BASE;
gd->bd->bi_dram[0].size = CONFIG_SYS_RAM_SIZE;
rv = 0;
dram_initialized = 1;
return rv;
}
