/** * The T30 requires some special clock initialization, including setting up * the dvc i2c, turning on mselect and selecting the G CPU cluster */ void t30_init_clocks(void) { struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE; u32 val; debug("t30_init_clocks entry\n"); /* Set active CPU cluster to G */ clrbits_le32(flow->cluster_control, 1 << 0); /* * Switch system clock to PLLP_OUT4 (108 MHz), AVP will now run * at 108 MHz. This is glitch free as only the source is changed, no * special precaution needed. */ val = (SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT) | (SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_IRQ_SOURCE_SHIFT) | (SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_RUN_SOURCE_SHIFT) | (SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_IDLE_SOURCE_SHIFT) | (SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT); writel(val, &clkrst->crc_sclk_brst_pol); writel(SUPER_SCLK_ENB_MASK, &clkrst->crc_super_sclk_div); val = (0 << CLK_SYS_RATE_HCLK_DISABLE_SHIFT) | (1 << CLK_SYS_RATE_AHB_RATE_SHIFT) | (0 << CLK_SYS_RATE_PCLK_DISABLE_SHIFT) | (0 << CLK_SYS_RATE_APB_RATE_SHIFT); writel(val, &clkrst->crc_clk_sys_rate); /* Put i2c, mselect in reset and enable clocks */ reset_set_enable(PERIPH_ID_DVC_I2C, 1); clock_set_enable(PERIPH_ID_DVC_I2C, 1); reset_set_enable(PERIPH_ID_MSELECT, 1); clock_set_enable(PERIPH_ID_MSELECT, 1); /* Switch MSELECT clock to PLLP (00) and use a divisor of 2 */ clock_ll_set_source_divisor(PERIPH_ID_MSELECT, 0, 2); /* * Our high-level clock routines are not available prior to * relocation. We use the low-level functions which require a * hard-coded divisor. Use CLK_M with divide by (n + 1 = 17) */ clock_ll_set_source_divisor(PERIPH_ID_DVC_I2C, 3, 16); /* * Give clocks time to stabilize, then take i2c and mselect out of * reset */ udelay(1000); reset_set_enable(PERIPH_ID_DVC_I2C, 0); reset_set_enable(PERIPH_ID_MSELECT, 0); }
/** * The T30 requires some special clock initialization, including setting up * the dvc i2c, turning on mselect and selecting the G CPU cluster */ void t30_init_clocks(void) { struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE; u32 val; debug("t30_init_clocks entry\n"); /* Set active CPU cluster to G */ clrbits_le32(flow->cluster_control, 1 << 0); writel(SUPER_SCLK_ENB_MASK, &clkrst->crc_super_sclk_div); val = (0 << CLK_SYS_RATE_HCLK_DISABLE_SHIFT) | (1 << CLK_SYS_RATE_AHB_RATE_SHIFT) | (0 << CLK_SYS_RATE_PCLK_DISABLE_SHIFT) | (0 << CLK_SYS_RATE_APB_RATE_SHIFT); writel(val, &clkrst->crc_clk_sys_rate); /* Put i2c, mselect in reset and enable clocks */ reset_set_enable(PERIPH_ID_DVC_I2C, 1); clock_set_enable(PERIPH_ID_DVC_I2C, 1); reset_set_enable(PERIPH_ID_MSELECT, 1); clock_set_enable(PERIPH_ID_MSELECT, 1); /* Switch MSELECT clock to PLLP (00) and use a divisor of 2 */ clock_ll_set_source_divisor(PERIPH_ID_MSELECT, 0, 2); /* * Our high-level clock routines are not available prior to * relocation. We use the low-level functions which require a * hard-coded divisor. Use CLK_M with divide by (n + 1 = 17) */ clock_ll_set_source_divisor(PERIPH_ID_DVC_I2C, 3, 16); /* * Give clocks time to stabilize, then take i2c and mselect out of * reset */ udelay(1000); reset_set_enable(PERIPH_ID_DVC_I2C, 0); reset_set_enable(PERIPH_ID_MSELECT, 0); }
/** * The T114 requires some special clock initialization, including setting up * the DVC I2C, turning on MSELECT and selecting the G CPU cluster */ void t114_init_clocks(void) { struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE; u32 val; debug("t114_init_clocks entry\n"); /* Set active CPU cluster to G */ clrbits_le32(&flow->cluster_control, 1); /* * Switch system clock to PLLP_OUT4 (108 MHz), AVP will now run * at 108 MHz. This is glitch free as only the source is changed, no * special precaution needed. */ val = (SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT) | (SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_IRQ_SOURCE_SHIFT) | (SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_RUN_SOURCE_SHIFT) | (SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_IDLE_SOURCE_SHIFT) | (SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT); writel(val, &clkrst->crc_sclk_brst_pol); writel(SUPER_SCLK_ENB_MASK, &clkrst->crc_super_sclk_div); debug("Setting up PLLX\n"); init_pllx(); val = (1 << CLK_SYS_RATE_AHB_RATE_SHIFT); writel(val, &clkrst->crc_clk_sys_rate); /* Enable clocks to required peripherals. TBD - minimize this list */ debug("Enabling clocks\n"); clock_set_enable(PERIPH_ID_CACHE2, 1); clock_set_enable(PERIPH_ID_GPIO, 1); clock_set_enable(PERIPH_ID_TMR, 1); clock_set_enable(PERIPH_ID_RTC, 1); clock_set_enable(PERIPH_ID_CPU, 1); clock_set_enable(PERIPH_ID_EMC, 1); clock_set_enable(PERIPH_ID_I2C5, 1); clock_set_enable(PERIPH_ID_FUSE, 1); clock_set_enable(PERIPH_ID_PMC, 1); clock_set_enable(PERIPH_ID_APBDMA, 1); clock_set_enable(PERIPH_ID_MEM, 1); clock_set_enable(PERIPH_ID_IRAMA, 1); clock_set_enable(PERIPH_ID_IRAMB, 1); clock_set_enable(PERIPH_ID_IRAMC, 1); clock_set_enable(PERIPH_ID_IRAMD, 1); clock_set_enable(PERIPH_ID_CORESIGHT, 1); clock_set_enable(PERIPH_ID_MSELECT, 1); clock_set_enable(PERIPH_ID_EMC1, 1); clock_set_enable(PERIPH_ID_MC1, 1); clock_set_enable(PERIPH_ID_DVFS, 1); /* Switch MSELECT clock to PLLP (00) */ clock_ll_set_source(PERIPH_ID_MSELECT, 0); /* * Clock divider request for 102MHz would setup MSELECT clock as * 102MHz for PLLP base 408MHz */ clock_ll_set_source_divisor(PERIPH_ID_MSELECT, 0, (NVBL_PLLP_KHZ/102000)); /* I2C5 (DVC) gets CLK_M and a divisor of 17 */ clock_ll_set_source_divisor(PERIPH_ID_I2C5, 3, 16); /* Give clocks time to stabilize */ udelay(1000); /* Take required peripherals out of reset */ debug("Taking periphs out of reset\n"); reset_set_enable(PERIPH_ID_CACHE2, 0); reset_set_enable(PERIPH_ID_GPIO, 0); reset_set_enable(PERIPH_ID_TMR, 0); reset_set_enable(PERIPH_ID_COP, 0); reset_set_enable(PERIPH_ID_EMC, 0); reset_set_enable(PERIPH_ID_I2C5, 0); reset_set_enable(PERIPH_ID_FUSE, 0); reset_set_enable(PERIPH_ID_APBDMA, 0); reset_set_enable(PERIPH_ID_MEM, 0); reset_set_enable(PERIPH_ID_CORESIGHT, 0); reset_set_enable(PERIPH_ID_MSELECT, 0); reset_set_enable(PERIPH_ID_EMC1, 0); reset_set_enable(PERIPH_ID_MC1, 0); debug("t114_init_clocks exit\n"); }
/** * Tegra124 requires some special clock initialization, including setting up * the DVC I2C, turning on MSELECT and selecting the G CPU cluster */ void tegra124_init_clocks(void) { struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE; struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; u32 val; debug("%s entry\n", __func__); /* Set active CPU cluster to G */ clrbits_le32(&flow->cluster_control, 1); /* Change the oscillator drive strength */ val = readl(&clkrst->crc_osc_ctrl); val &= ~OSC_XOFS_MASK; val |= (OSC_DRIVE_STRENGTH << OSC_XOFS_SHIFT); writel(val, &clkrst->crc_osc_ctrl); /* Update same value in PMC_OSC_EDPD_OVER XOFS field for warmboot */ val = readl(&pmc->pmc_osc_edpd_over); val &= ~PMC_XOFS_MASK; val |= (OSC_DRIVE_STRENGTH << PMC_XOFS_SHIFT); writel(val, &pmc->pmc_osc_edpd_over); /* Set HOLD_CKE_LOW_EN to 1 */ setbits_le32(&pmc->pmc_cntrl2, HOLD_CKE_LOW_EN); debug("Setting up PLLX\n"); init_pllx(); val = (1 << CLK_SYS_RATE_AHB_RATE_SHIFT); writel(val, &clkrst->crc_clk_sys_rate); /* Enable clocks to required peripherals. TBD - minimize this list */ debug("Enabling clocks\n"); clock_set_enable(PERIPH_ID_CACHE2, 1); clock_set_enable(PERIPH_ID_GPIO, 1); clock_set_enable(PERIPH_ID_TMR, 1); clock_set_enable(PERIPH_ID_CPU, 1); clock_set_enable(PERIPH_ID_EMC, 1); clock_set_enable(PERIPH_ID_I2C5, 1); clock_set_enable(PERIPH_ID_APBDMA, 1); clock_set_enable(PERIPH_ID_MEM, 1); clock_set_enable(PERIPH_ID_CORESIGHT, 1); clock_set_enable(PERIPH_ID_MSELECT, 1); clock_set_enable(PERIPH_ID_DVFS, 1); /* * Set MSELECT clock source as PLLP (00), and ask for a clock * divider that would set the MSELECT clock at 102MHz for a * PLLP base of 408MHz. */ clock_ll_set_source_divisor(PERIPH_ID_MSELECT, 0, CLK_DIVIDER(NVBL_PLLP_KHZ, 102000)); /* Give clock time to stabilize */ udelay(IO_STABILIZATION_DELAY); /* I2C5 (DVC) gets CLK_M and a divisor of 17 */ clock_ll_set_source_divisor(PERIPH_ID_I2C5, 3, 16); /* Give clock time to stabilize */ udelay(IO_STABILIZATION_DELAY); /* Take required peripherals out of reset */ debug("Taking periphs out of reset\n"); reset_set_enable(PERIPH_ID_CACHE2, 0); reset_set_enable(PERIPH_ID_GPIO, 0); reset_set_enable(PERIPH_ID_TMR, 0); reset_set_enable(PERIPH_ID_COP, 0); reset_set_enable(PERIPH_ID_EMC, 0); reset_set_enable(PERIPH_ID_I2C5, 0); reset_set_enable(PERIPH_ID_APBDMA, 0); reset_set_enable(PERIPH_ID_MEM, 0); reset_set_enable(PERIPH_ID_CORESIGHT, 0); reset_set_enable(PERIPH_ID_MSELECT, 0); reset_set_enable(PERIPH_ID_DVFS, 0); debug("%s exit\n", __func__); }