static int get_sda(void) { unsigned char tmp; tmp = clps_readb(PDDR); return (tmp & SDA) ? 1 : 0; }
static void make_sda_input(void) { unsigned char tmp; tmp = clps_readb(PDDDR); tmp |= SDA; clps_writeb(tmp, PDDDR); }
static void make_scl_sda_outputs(void) { unsigned char tmp; tmp = clps_readb(PDDDR); tmp &= ~(SCL | SDA); clps_writeb(tmp, PDDDR); }
int setup_cs43l42(void) { volatile long u; volatile char port_d; printk("cs43l42: init dac\n"); port_d = clps_readb(PDDR) & ~(SCL | SDA); /* enable codec_en# */ reset_cs43l42(); /* make SDA & SCL outputs */ make_scl_sda_outputs(); /* * enable the two wire serial interface on the CS43L42 * by setting the CP_EN bit (bit 0) of register 1 */ cs43l42_i2c_write(ADDR_CS43L42, CS43L42_PWRCTL, 0xd2); /* set the data format to left justified */ cs43l42_i2c_write(ADDR_CS43L42, 0x0b, 0x02); /* power on the DAC */ cs43l42_i2c_write(ADDR_CS43L42, CS43L42_PWRCTL, 0xd0); /* delay while the DAC initializes */ for(u = 0; u < 15; u++) udelay(5); cs43l42_i2c_write(ADDR_CS43L42, 2, 0xf1); cs43l42_i2c_write(ADDR_CS43L42, 3, 0xf1); #if 0 cs43l42_dump_regs(); printk("syscon1 %08x\n", clps_readl(SYSCON1)); printk("syscon2 %08x\n", clps_readl(SYSCON2)); printk("syscon3 %08x\n", clps_readl(SYSCON3)); #endif /* restore original port D value */ port_d |= clps_readb(PDDR); clps_writeb(port_d, PDDR); printk("cs43l42: init dac complete\n"); return 0; }
static void set_sda(int val) { unsigned char tmp; tmp = clps_readb(PDDR); if (val) tmp |= SDA; else tmp &= ~SDA; clps_writeb(tmp, PDDR); }
/* * hardware specific access to control-lines */ static void ep7312_hwcontrol(struct mtd_info *mtd, int cmd) { switch(cmd) { case NAND_CTL_SETCLE: clps_writeb(clps_readb(ep7312_pxdr) | 0x10, ep7312_pxdr); break; case NAND_CTL_CLRCLE: clps_writeb(clps_readb(ep7312_pxdr) & ~0x10, ep7312_pxdr); break; case NAND_CTL_SETALE: clps_writeb(clps_readb(ep7312_pxdr) | 0x20, ep7312_pxdr); break; case NAND_CTL_CLRALE: clps_writeb(clps_readb(ep7312_pxdr) & ~0x20, ep7312_pxdr); break; case NAND_CTL_SETNCE: clps_writeb((clps_readb(ep7312_pxdr) | 0x80) & ~0x40, ep7312_pxdr); break; case NAND_CTL_CLRNCE: clps_writeb((clps_readb(ep7312_pxdr) | 0x80) | 0x40, ep7312_pxdr); break; } }
/* * hardware specific access to control-lines * * NAND_NCE: bit 0 -> bit 6 (bit 7 = 1) * NAND_CLE: bit 1 -> bit 4 * NAND_ALE: bit 2 -> bit 5 */ static void ep7312_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) { struct nand_chip *chip = mtd->priv; if (ctrl & NAND_CTRL_CHANGE) { unsigned char bits = 0x80; bits |= (ctrl & (NAND_CLE | NAND_ALE)) << 3; bits |= (ctrl & NAND_NCE) ? 0x00 : 0x40; clps_writeb((clps_readb(ep7312_pxdr) & 0xF0) | bits, ep7312_pxdr); } if (cmd != NAND_CMD_NONE) writeb(cmd, chip->IO_ADDR_W); }
static void p720t_leds_event(led_event_t ledevt) { unsigned long flags; u32 pddr; local_irq_save(flags); switch(ledevt) { case led_idle_start: break; case led_idle_end: break; case led_timer: pddr = clps_readb(PDDR); clps_writeb(pddr ^ 1, PDDR); break; default: break; } local_irq_restore(flags); }
unsigned char kgdb_serial_getchar(void) { while (clps_readl(KGDB_SYSFLG) & 0x00400000); return clps_readb(KGDB_UART); }