int amdpm_activate(struct device *self, int act) { struct amdpm_softc *sc = (struct amdpm_softc *)self; int rv = 0; switch (act) { case DVACT_RESUME: if (timeout_initialized(&sc->sc_rnd_ch)) { pcireg_t cfg_reg; /* Restart the AMD PBC768_PMC/8111_PMC RNG */ cfg_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMDPM_CONFREG); pci_conf_write(sc->sc_pc, sc->sc_tag, AMDPM_CONFREG, cfg_reg | AMDPM_RNGEN); } rv = config_activate_children(self, act); break; default: rv = config_activate_children(self, act); break; } return (rv); }
int radeondrm_activate_kms(struct device *self, int act) { struct radeon_device *rdev = (struct radeon_device *)self; int rv = 0; if (rdev->ddev == NULL) return (0); switch (act) { case DVACT_QUIESCE: rv = config_activate_children(self, act); radeon_suspend_kms(rdev->ddev); break; case DVACT_SUSPEND: break; case DVACT_RESUME: break; case DVACT_WAKEUP: radeon_resume_kms(rdev->ddev); rv = config_activate_children(self, act); break; } return (rv); }
int glxpcib_activate(struct device *self, int act) { #ifndef SMALL_KERNEL struct glxpcib_softc *sc = (struct glxpcib_softc *)self; uint i; #endif int rv = 0; switch (act) { case DVACT_SUSPEND: #ifndef SMALL_KERNEL if (sc->sc_wdog) { sc->sc_wdog_period = bus_space_read_2(sc->sc_iot, sc->sc_ioh, AMD5536_MFGPT0_CMP2); glxpcib_wdogctl_cb(sc, 0); } #endif rv = config_activate_children(self, act); #ifndef SMALL_KERNEL for (i = 0; i < nitems(glxpcib_msrlist); i++) sc->sc_msrsave[i] = rdmsr(glxpcib_msrlist[i]); #endif break; case DVACT_RESUME: #ifndef SMALL_KERNEL if (sc->sc_wdog) glxpcib_wdogctl_cb(sc, sc->sc_wdog_period); for (i = 0; i < nitems(glxpcib_msrlist); i++) wrmsr(glxpcib_msrlist[i], sc->sc_msrsave[i]); #endif rv = config_activate_children(self, act); break; case DVACT_POWERDOWN: #ifndef SMALL_KERNEL if (sc->sc_wdog) wdog_shutdown(self); #endif rv = config_activate_children(self, act); break; default: rv = config_activate_children(self, act); break; } return (rv); }
int sili_pci_activate(struct device *self, int act) { struct sili_softc *sc = (struct sili_softc *)self; int rv = 0; switch (act) { case DVACT_RESUME: sili_resume(sc); rv = config_activate_children(self, act); break; default: rv = config_activate_children(self, act); break; } return (rv); }
int esp_activate(struct device *self, int act) { struct ncr53c9x_softc *sc = self; int rv = 0; switch (act) { case DVACT_POWERDOWN: rv = config_activate_children(self, act); NCRCMD(sc, NCRCMD_RSTSCSI); break; default: rv = config_activate_children(self, act); break; } return (rv); }
int tcpcib_activate(struct device *self, int act) { struct tcpcib_softc *sc = (struct tcpcib_softc *)self; int rv = 0; switch (act) { case DVACT_SUSPEND: rv = config_activate_children(self, act); /* Watchdog is running, disable it */ if (sc->sc_active & E600_WDT_ACTIVE && sc->sc_wdt_period != 0) tcpcib_wdt_stop(sc); break; case DVACT_RESUME: if (sc->sc_active & E600_WDT_ACTIVE) { /* * Watchdog was running prior to suspend so reenable * it, otherwise make sure it stays disabled */ if (sc->sc_wdt_period != 0) { tcpcib_wdt_init(sc, sc->sc_wdt_period); tcpcib_wdt_start(sc); } else tcpcib_wdt_stop(sc); } if (sc->sc_active & E600_HPET_ACTIVE) bus_space_write_4(sc->sc_hpet_iot, sc->sc_hpet_ioh, E600_HPET_GC, E600_HPET_GC_ENABLE); rv = config_activate_children(self, act); break; case DVACT_POWERDOWN: if (sc->sc_active & E600_WDT_ACTIVE) wdog_shutdown(self); rv = config_activate_children(self, act); break; default: rv = config_activate_children(self, act); break; } return (rv); }
int eap_activate(struct device *self, int act) { struct eap_softc *sc = (struct eap_softc *)self; int rv = 0; switch (act) { case DVACT_QUIESCE: rv = config_activate_children(self, act); break; case DVACT_SUSPEND: break; case DVACT_RESUME: eap_resume(sc); rv = config_activate_children(self, act); break; case DVACT_DEACTIVATE: break; } return (rv); }
int pvbus_activate(struct device *self, int act) { int rv = 0; switch (act) { case DVACT_SUSPEND: rv = config_activate_children(self, act); break; case DVACT_RESUME: rv = config_activate_children(self, act); break; case DVACT_POWERDOWN: rv = config_activate_children(self, act); break; default: rv = config_activate_children(self, act); break; } return (rv); }
int pchbactivate(struct device *self, int act) { struct pchb_softc *sc = (struct pchb_softc *)self; int rv = 0; switch (act) { case DVACT_RESUME: /* re-enable RNG, if we have it */ if (sc->sc_rng_active) bus_space_write_1(sc->sc_bt, sc->sc_bh, I82802_RNG_HWST, bus_space_read_1(sc->sc_bt, sc->sc_bh, I82802_RNG_HWST) | I82802_RNG_HWST_ENABLE); rv = config_activate_children(self, act); break; default: rv = config_activate_children(self, act); break; } return (rv); }
int nfe_activate(struct device *self, int act) { struct nfe_softc *sc = (struct nfe_softc *)self; struct ifnet *ifp = &sc->sc_arpcom.ac_if; int rv = 0; switch (act) { case DVACT_SUSPEND: if (ifp->if_flags & IFF_RUNNING) nfe_stop(ifp, 0); rv = config_activate_children(self, act); break; case DVACT_RESUME: if (ifp->if_flags & IFF_UP) nfe_init(ifp); break; default: rv = config_activate_children(self, act); break; } return (rv); }
int sili_pci_activate(struct device *self, int act) { struct sili_softc *sc = (struct sili_softc *)self; int rv = 0; switch (act) { case DVACT_QUIESCE: rv = config_activate_children(self, act); break; case DVACT_SUSPEND: rv = config_activate_children(self, act); break; case DVACT_POWERDOWN: rv = config_activate_children(self, act); break; case DVACT_RESUME: sili_resume(sc); rv = config_activate_children(self, act); break; } return (rv); }
int eap_activate(struct device *self, int act) { struct eap_softc *sc = (struct eap_softc *)self; switch (act) { case DVACT_RESUME: eap_resume(sc); break; default: break; } return (config_activate_children(self, act)); }
int ciss_activate(struct device *self, int act) { int ret = 0; ret = config_activate_children(self, act); switch (act) { case DVACT_POWERDOWN: ciss_shutdown(self); break; } return (ret); }
int imc_activate(struct device *self, int act) { int rv = 0; switch (act) { case DVACT_POWERDOWN: #ifndef SMALL_KERNEL wdog_shutdown(self); #endif rv = config_activate_children(self, act); break; } return (rv); }
int lcd_activate(struct device *self, int act) { struct pxa2x0_lcd_softc *sc = (struct pxa2x0_lcd_softc *)self; int ret = 0; switch (act) { case DVACT_SUSPEND: lcd_set_brightness(0); pxa2x0_lcd_suspend(sc); break; case DVACT_RESUME: pxa2x0_lcd_resume(sc); lcd_set_brightness(lcd_get_brightness()); break; default: ret = config_activate_children(self, act); break; } return (ret); }
int ppbactivate(struct device *self, int act) { struct ppb_softc *sc = (void *)self; pci_chipset_tag_t pc = sc->sc_pc; pcitag_t tag = sc->sc_tag; pcireg_t blr, reg; int off, rv = 0; switch (act) { case DVACT_QUIESCE: rv = config_activate_children(self, act); break; case DVACT_SUSPEND: rv = config_activate_children(self, act); /* Save registers that may get lost. */ sc->sc_csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); sc->sc_bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); sc->sc_bir = pci_conf_read(pc, tag, PPB_REG_BUSINFO); sc->sc_bcr = pci_conf_read(pc, tag, PPB_REG_BRIDGECONTROL); sc->sc_int = pci_conf_read(pc, tag, PCI_INTERRUPT_REG); if (sc->sc_cap_off) sc->sc_slcsr = pci_conf_read(pc, tag, sc->sc_cap_off + PCI_PCIE_SLCSR); if (pci_get_capability(pc, tag, PCI_CAP_MSI, &off, ®)) { sc->sc_msi_ma = pci_conf_read(pc, tag, off + PCI_MSI_MA); if (reg & PCI_MSI_MC_C64) { sc->sc_msi_mau32 = pci_conf_read(pc, tag, off + PCI_MSI_MAU32); sc->sc_msi_md = pci_conf_read(pc, tag, off + PCI_MSI_MD64); } else { sc->sc_msi_md = pci_conf_read(pc, tag, off + PCI_MSI_MD32); } sc->sc_msi_mc = reg; } if (pci_dopm) { /* Place the bridge into D3. */ sc->sc_pmcsr_state = pci_get_powerstate(pc, tag); pci_set_powerstate(pc, tag, PCI_PMCSR_STATE_D3); } break; case DVACT_RESUME: if (pci_dopm) { /* Restore power. */ pci_set_powerstate(pc, tag, sc->sc_pmcsr_state); } /* Restore the registers saved above. */ pci_conf_write(pc, tag, PCI_BHLC_REG, sc->sc_bhlcr); pci_conf_write(pc, tag, PPB_REG_BUSINFO, sc->sc_bir); pci_conf_write(pc, tag, PPB_REG_BRIDGECONTROL, sc->sc_bcr); pci_conf_write(pc, tag, PCI_INTERRUPT_REG, sc->sc_int); if (sc->sc_cap_off) pci_conf_write(pc, tag, sc->sc_cap_off + PCI_PCIE_SLCSR, sc->sc_slcsr); /* Restore I/O window. */ blr = pci_conf_read(pc, tag, PPB_REG_IOSTATUS); blr &= 0xffff0000; blr |= sc->sc_iolimit & PPB_IO_MASK; blr |= (sc->sc_iobase >> PPB_IO_SHIFT); pci_conf_write(pc, tag, PPB_REG_IOSTATUS, blr); blr = (sc->sc_iobase & 0xffff0000) >> 16; blr |= sc->sc_iolimit & 0xffff0000; pci_conf_write(pc, tag, PPB_REG_IO_HI, blr); /* Restore memory mapped I/O window. */ blr = sc->sc_memlimit & PPB_MEM_MASK; blr |= (sc->sc_membase >> PPB_MEM_SHIFT); pci_conf_write(pc, tag, PPB_REG_MEM, blr); /* Restore prefetchable MMI/O window. */ blr = sc->sc_pmemlimit & PPB_MEM_MASK; blr |= (sc->sc_pmembase >> PPB_MEM_SHIFT); pci_conf_write(pc, tag, PPB_REG_PREFMEM, blr); #ifdef __LP64__ pci_conf_write(pc, tag, PPB_REG_PREFBASE_HI32, sc->sc_pmembase >> 32); pci_conf_write(pc, tag, PPB_REG_PREFLIM_HI32, sc->sc_pmemlimit >> 32); #endif if (pci_get_capability(pc, tag, PCI_CAP_MSI, &off, ®)) { pci_conf_write(pc, tag, off + PCI_MSI_MA, sc->sc_msi_ma); if (reg & PCI_MSI_MC_C64) { pci_conf_write(pc, tag, off + PCI_MSI_MAU32, sc->sc_msi_mau32); pci_conf_write(pc, tag, off + PCI_MSI_MD64, sc->sc_msi_md); } else { pci_conf_write(pc, tag, off + PCI_MSI_MD32, sc->sc_msi_md); } pci_conf_write(pc, tag, off + PCI_MSI_MC, sc->sc_msi_mc); } /* * Restore command register last to avoid exposing * uninitialised windows. */ reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, (reg & 0xffff0000) | (sc->sc_csr & 0x0000ffff)); rv = config_activate_children(self, act); break; } return (rv); }
int scsibusactivate(struct device *dev, enum devact act) { return (config_activate_children(dev, act)); }