static void set_control_vbyone(Lcd_Config_t *pConf) { int lane, byte, region, hsize, vsize;//color_fmt, int vin_color, vin_bpp; hsize = 3840;//pConf->lcd_basic.h_active; vsize = 2160;//pConf->lcd_basic.v_active; lane = 8;//byte_num; byte = 4;//byte_num; region = 2;//region_num; vin_color = 4; vin_bpp = 0; printf("Set VbyOne PIN MUX ......\n"); aml_set_reg32_bits(P_PERIPHS_PIN_MUX_3,3,8,2); // set Vbyone printf("VbyOne Configuration ......\n"); //set_vbyone_vfmt(vin_color,vin_bpp); aml_set_reg32_bits(P_VBO_VIN_CTRL, vin_color, VBO_VIN_PACK_BIT,VBO_VIN_PACK_WID); aml_set_reg32_bits(P_VBO_VIN_CTRL,vin_bpp, VBO_VIN_BPP_BIT,VBO_VIN_BPP_WID); config_vbyone(lane, byte, region, hsize, vsize); set_vbyone_sync_pol(0, 0); //set hsync/vsync polarity to let the polarity is low active inside the VbyOne // below line copy from simulation aml_set_reg32_bits(P_VBO_VIN_CTRL, 1, 0, 2); //gate the input when vsync asserted ///aml_set_reg32(P_VBO_VBK_CTRL_0,0x13); //aml_set_reg32(P_VBO_VBK_CTRL_1,0x56); //aml_set_reg32(P_VBO_HBK_CTRL,0x3478); //aml_set_reg32_bits(P_VBO_PXL_CTRL,0x2,VBO_PXL_CTR0_BIT,VBO_PXL_CTR0_WID); //aml_set_reg32_bits(P_VBO_PXL_CTRL,0x3,VBO_PXL_CTR1_BIT,VBO_PXL_CTR1_WID); //set_vbyone_ctlbits(1,0,0); //set fifo_clk_sel: 3 for 10-bits aml_set_reg32_bits(P_HHI_LVDS_TX_PHY_CNTL0,3,6,2); //PAD select: if ((lane == 1) || (lane == 2)) { aml_set_reg32_bits(P_LCD_PORT_SWAP,1,9,2); } else if (lane == 4) { aml_set_reg32_bits(P_LCD_PORT_SWAP,2,9,2); } else { aml_set_reg32_bits(P_LCD_PORT_SWAP,0,9,2); } //aml_set_reg32_bits(P_LCD_PORT_SWAP, 1, 8, 1);//reverse lane output order // Mux pads in combo-phy: 0 for dsi; 1 for lvds or vbyone; 2 for edp aml_write_reg32(P_HHI_DSI_LVDS_EDP_CNTL0, 0x1); // Select vbyone in combo-phy aml_set_reg32_bits(P_VBO_CTRL_L, 1, VBO_ENABLE_BIT, VBO_EBABLE_WID); //force vencl clk enable, otherwise, it might auto turn off by mipi DSI printf("VbyOne is In Normal Status ......\n"); }
//=============================================================== void set_VX1_output(int lane_num, int byte_num, int region_num, int color_fmt, int hsize, int vsize) { int vin_color,vin_bpp; switch (color_fmt) { case 0: //SDVT_VBYONE_18BPP_RGB vin_color = 4; vin_bpp = 2; break; case 1: //SDVT_VBYONE_18BPP_YCBCR444 vin_color = 0; vin_bpp = 2; break; case 2: //SDVT_VBYONE_24BPP_RGB vin_color = 4; vin_bpp = 1; break; case 3: //SDVT_VBYONE_24BPP_YCBCR444 vin_color = 0; vin_bpp = 1; break; case 4: //SDVT_VBYONE_30BPP_RGB vin_color = 4; vin_bpp = 0; break; case 5: //SDVT_VBYONE_30BPP_YCBCR444 vin_color = 0; vin_bpp = 0; break; default: LOGE(TAG_VBY, "Error VBYONE_COLOR_FORMAT!\n"); return; } //PIN_MUX for VX1 LOGD(TAG_VBY, "Set VbyOne PIN MUX ......\n"); Wr_reg_bits(PERIPHS_PIN_MUX_3,3,8,2); //set Vbyone LOGD(TAG_VBY, "VbyOne Configuration ......\n"); set_vbyone_vfmt(vin_color,vin_bpp); config_vbyone(lane_num,byte_num,region_num,hsize,vsize,0); set_vbyone_sync_pol(1,1); //set hsync/vsync polarity to let the polarity is low active inside the VbyOne //PAD select: if((lane_num == 1) || (lane_num==2)) { Wr_reg_bits(VBO_LANE_SWAP,1,9,2); } else if(lane_num ==4) { Wr_reg_bits(VBO_LANE_SWAP,2,9,2); } else { Wr_reg_bits(VBO_LANE_SWAP,0,9,2); } Wr_reg_bits(VBO_LANE_SWAP,1,8,1);//reverse lane output order set_vpu_output_mode(1); //Vbyone //LOGW(TAG_VBY, "Waiting for VbyOne CDR/ALN......\n"); //while((Rd(VBO_RO_STATUS)&(1<<5))==0) //{}; LOGD(TAG_VBY, "VbyOne is In Normal Status ......\n"); }