/* void DDR2_EMIF_Config(void); */
static void config_am335x_ddr2(void)
{
int data_macro_0 = 0;
int data_macro_1 = 1;
enable_ddr_clocks();
config_vtp();
Cmd_Macro_Config();
Data_Macro_Config(data_macro_0);
Data_Macro_Config(data_macro_1);
__raw_writel(PHY_RANK0_DELAY, DATA0_RANK0_DELAYS_0);
__raw_writel(PHY_RANK0_DELAY, DATA1_RANK0_DELAYS_0);
__raw_writel(DDR_IOCTRL_VALUE, DDR_CMD0_IOCTRL);
__raw_writel(DDR_IOCTRL_VALUE, DDR_CMD1_IOCTRL);
__raw_writel(DDR_IOCTRL_VALUE, DDR_CMD2_IOCTRL);
__raw_writel(DDR_IOCTRL_VALUE, DDR_DATA0_IOCTRL);
__raw_writel(DDR_IOCTRL_VALUE, DDR_DATA1_IOCTRL);
__raw_writel(__raw_readl(DDR_IO_CTRL) & 0xefffffff, DDR_IO_CTRL);
__raw_writel(__raw_readl(DDR_CKE_CTRL) | 0x00000001, DDR_CKE_CTRL);
config_emif_ddr2();
}
void config_ddr(short ddr_type)
{
int ddr_pll, ioctrl_val;
const struct emif_regs *emif_regs;
const struct ddr_data *ddr_data;
const struct cmd_control *cmd_ctrl_data;
if (ddr_type == EMIF_REG_SDRAM_TYPE_DDR2) {
ddr_pll = 266;
cmd_ctrl_data = &ddr2_cmd_ctrl_data;
ddr_data = &ddr2_data;
ioctrl_val = DDR2_IOCTRL_VALUE;
emif_regs = &ddr2_emif_reg_data;
} else if (ddr_type == EMIF_REG_SDRAM_TYPE_DDR3) {
ddr_pll = 303;
ioctrl_val = DDR3_IOCTRL_VALUE;
cmd_ctrl_data = &ddr3_cmd_ctrl_data;
if (board_is_evm_15_or_later()) {
ddr_data = &ddr3_evm_data;
emif_regs = &ddr3_evm_emif_reg_data;
} else {
ddr_data = &ddr3_data;
emif_regs = &ddr3_emif_reg_data;
}
} else {
puts("Unknown memory type");
hang();
}
enable_emif_clocks();
ddr_pll_config(ddr_pll);
config_vtp();
config_cmd_ctrl(cmd_ctrl_data);
config_ddr_data(0, ddr_data);
config_ddr_data(1, ddr_data);
config_io_ctrl(ioctrl_val);
/* Set CKE to be controlled by EMIF/DDR PHY */
writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);
/* Program EMIF instance */
config_ddr_phy(emif_regs);
set_sdram_timings(emif_regs);
config_sdram(emif_regs);
}
void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs,
const struct ddr_data *data, const struct cmd_control *ctrl,
const struct emif_regs *regs, int nr)
{
ddr_pll_config(pll);
#ifndef CONFIG_TI816X
config_vtp(nr);
#endif
config_cmd_ctrl(ctrl, nr);
config_ddr_data(data, nr);
#ifdef CONFIG_AM33XX
config_io_ctrl(ioregs);
/* Set CKE to be controlled by EMIF/DDR PHY */
writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);
#endif
#ifdef CONFIG_AM43XX
writel(readl(&cm_device->cm_dll_ctrl) & ~0x1, &cm_device->cm_dll_ctrl);
while ((readl(&cm_device->cm_dll_ctrl) & CM_DLL_READYST) == 0)
;
config_io_ctrl(ioregs);
/* Set CKE to be controlled by EMIF/DDR PHY */
writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);
/* Allow EMIF to control DDR_RESET */
writel(0x00000000, &ddrctrl->ddrioctrl);
#endif
/* Program EMIF instance */
config_ddr_phy(regs, nr);
set_sdram_timings(regs, nr);
if (get_emif_rev(EMIF1_BASE) == EMIF_4D5)
config_sdram_emif4d5(regs, nr);
else
config_sdram(regs, nr);
}
void config_ddr(unsigned int pll, unsigned int ioctrl,
const struct ddr_data *data, const struct cmd_control *ctrl,
const struct emif_regs *regs)
{
enable_emif_clocks();
ddr_pll_config(pll);
config_vtp();
config_cmd_ctrl(ctrl);
config_ddr_data(0, data);
config_ddr_data(1, data);
config_io_ctrl(ioctrl);
/* Set CKE to be controlled by EMIF/DDR PHY */
writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);
/* Program EMIF instance */
config_ddr_phy(regs);
set_sdram_timings(regs);
config_sdram(regs);
}
