예제 #1
0
static int clk_sys_event(struct snd_soc_dapm_widget *w,
			 struct snd_kcontrol *kcontrol, int event)
{
	struct snd_soc_codec *codec = w->codec;
	struct wm9081_priv *wm9081 = codec->private_data;

	/* This should be done on init() for bypass paths */
	switch (wm9081->sysclk_source) {
	case WM9081_SYSCLK_MCLK:
		dev_dbg(codec->dev, "Using %dHz MCLK\n", wm9081->mclk_rate);
		break;
	case WM9081_SYSCLK_FLL_MCLK:
		dev_dbg(codec->dev, "Using %dHz MCLK with FLL\n",
			wm9081->mclk_rate);
		break;
	default:
		dev_err(codec->dev, "System clock not configured\n");
		return -EINVAL;
	}

	switch (event) {
	case SND_SOC_DAPM_PRE_PMU:
		configure_clock(codec);
		break;

	case SND_SOC_DAPM_POST_PMD:
		/* Disable the FLL if it's running */
		wm9081_set_fll(codec, 0, 0, 0);
		break;
	}

	return 0;
}
예제 #2
0
static int clk_sys_event(struct snd_soc_dapm_widget *w,
			 struct snd_kcontrol *kcontrol, int event)
{
	struct snd_soc_codec *codec = w->codec;
	struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);

	
	switch (wm9081->sysclk_source) {
	case WM9081_SYSCLK_MCLK:
		dev_dbg(codec->dev, "Using %dHz MCLK\n", wm9081->mclk_rate);
		break;
	case WM9081_SYSCLK_FLL_MCLK:
		dev_dbg(codec->dev, "Using %dHz MCLK with FLL\n",
			wm9081->mclk_rate);
		break;
	default:
		dev_err(codec->dev, "System clock not configured\n");
		return -EINVAL;
	}

	switch (event) {
	case SND_SOC_DAPM_PRE_PMU:
		configure_clock(codec);
		break;

	case SND_SOC_DAPM_POST_PMD:
		
		wm9081_set_fll(codec, 0, 0, 0);
		break;
	}

	return 0;
}
예제 #3
0
static int clk_sys_event(struct snd_soc_dapm_widget *w,
			 struct snd_kcontrol *kcontrol, int event)
{
	struct snd_soc_codec *codec = w->codec;

	switch (event) {
	case SND_SOC_DAPM_PRE_PMU:
		return configure_clock(codec);

	case SND_SOC_DAPM_POST_PMD:
		break;
	}

	return 0;
}
예제 #4
0
static int wm8993_hw_params(struct snd_pcm_substream *substream,
			    struct snd_pcm_hw_params *params,
			    struct snd_soc_dai *dai)
{
	struct snd_soc_codec *codec = dai->codec;
	struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec);
	int ret, i, best, best_val, cur_val;
	unsigned int clocking1, clocking3, aif1, aif4;

	clocking1 = snd_soc_read(codec, WM8993_CLOCKING_1);
	clocking1 &= ~WM8993_BCLK_DIV_MASK;

	clocking3 = snd_soc_read(codec, WM8993_CLOCKING_3);
	clocking3 &= ~(WM8993_CLK_SYS_RATE_MASK | WM8993_SAMPLE_RATE_MASK);

	aif1 = snd_soc_read(codec, WM8993_AUDIO_INTERFACE_1);
	aif1 &= ~WM8993_AIF_WL_MASK;

	aif4 = snd_soc_read(codec, WM8993_AUDIO_INTERFACE_4);
	aif4 &= ~WM8993_LRCLK_RATE_MASK;

	/* What BCLK do we need? */
	wm8993->fs = params_rate(params);
	wm8993->bclk = 2 * wm8993->fs;
	if (wm8993->tdm_slots) {
		dev_dbg(codec->dev, "Configuring for %d %d bit TDM slots\n",
			wm8993->tdm_slots, wm8993->tdm_width);
		wm8993->bclk *= wm8993->tdm_width * wm8993->tdm_slots;
	} else {
		switch (params_format(params)) {
		case SNDRV_PCM_FORMAT_S16_LE:
			wm8993->bclk *= 16;
			break;
		case SNDRV_PCM_FORMAT_S20_3LE:
			wm8993->bclk *= 20;
			aif1 |= 0x8;
			break;
		case SNDRV_PCM_FORMAT_S24_LE:
			wm8993->bclk *= 24;
			aif1 |= 0x10;
			break;
		case SNDRV_PCM_FORMAT_S32_LE:
			wm8993->bclk *= 32;
			aif1 |= 0x18;
			break;
		default:
			return -EINVAL;
		}
	}

	dev_dbg(codec->dev, "Target BCLK is %dHz\n", wm8993->bclk);

	ret = configure_clock(codec);
	if (ret != 0)
		return ret;

	/* Select nearest CLK_SYS_RATE */
	best = 0;
	best_val = abs((wm8993->sysclk_rate / clk_sys_rates[0].ratio)
		       - wm8993->fs);
	for (i = 1; i < ARRAY_SIZE(clk_sys_rates); i++) {
		cur_val = abs((wm8993->sysclk_rate /
			       clk_sys_rates[i].ratio) - wm8993->fs);
		if (cur_val < best_val) {
			best = i;
			best_val = cur_val;
		}
	}
	dev_dbg(codec->dev, "Selected CLK_SYS_RATIO of %d\n",
		clk_sys_rates[best].ratio);
	clocking3 |= (clk_sys_rates[best].clk_sys_rate
		      << WM8993_CLK_SYS_RATE_SHIFT);

	/* SAMPLE_RATE */
	best = 0;
	best_val = abs(wm8993->fs - sample_rates[0].rate);
	for (i = 1; i < ARRAY_SIZE(sample_rates); i++) {
		/* Closest match */
		cur_val = abs(wm8993->fs - sample_rates[i].rate);
		if (cur_val < best_val) {
			best = i;
			best_val = cur_val;
		}
	}
	dev_dbg(codec->dev, "Selected SAMPLE_RATE of %dHz\n",
		sample_rates[best].rate);
	clocking3 |= (sample_rates[best].sample_rate
		      << WM8993_SAMPLE_RATE_SHIFT);

	/* BCLK_DIV */
	best = 0;
	best_val = INT_MAX;
	for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
		cur_val = ((wm8993->sysclk_rate * 10) / bclk_divs[i].div)
			- wm8993->bclk;
		if (cur_val < 0) /* Table is sorted */
			break;
		if (cur_val < best_val) {
			best = i;
			best_val = cur_val;
		}
	}
	wm8993->bclk = (wm8993->sysclk_rate * 10) / bclk_divs[best].div;
	dev_dbg(codec->dev, "Selected BCLK_DIV of %d for %dHz BCLK\n",
		bclk_divs[best].div, wm8993->bclk);
	clocking1 |= bclk_divs[best].bclk_div << WM8993_BCLK_DIV_SHIFT;

	/* LRCLK is a simple fraction of BCLK */
	dev_dbg(codec->dev, "LRCLK_RATE is %d\n", wm8993->bclk / wm8993->fs);
	aif4 |= wm8993->bclk / wm8993->fs;

	snd_soc_write(codec, WM8993_CLOCKING_1, clocking1);
	snd_soc_write(codec, WM8993_CLOCKING_3, clocking3);
	snd_soc_write(codec, WM8993_AUDIO_INTERFACE_1, aif1);
	snd_soc_write(codec, WM8993_AUDIO_INTERFACE_4, aif4);

	/* ReTune Mobile? */
	if (wm8993->pdata.num_retune_configs) {
		u16 eq1 = snd_soc_read(codec, WM8993_EQ1);
		struct wm8993_retune_mobile_setting *s;

		best = 0;
		best_val = abs(wm8993->pdata.retune_configs[0].rate
			       - wm8993->fs);
		for (i = 0; i < wm8993->pdata.num_retune_configs; i++) {
			cur_val = abs(wm8993->pdata.retune_configs[i].rate
				      - wm8993->fs);
			if (cur_val < best_val) {
				best_val = cur_val;
				best = i;
			}
		}
		s = &wm8993->pdata.retune_configs[best];

		dev_dbg(codec->dev, "ReTune Mobile %s tuned for %dHz\n",
			s->name, s->rate);

		/* Disable EQ while we reconfigure */
		snd_soc_update_bits(codec, WM8993_EQ1, WM8993_EQ_ENA, 0);

		for (i = 1; i < ARRAY_SIZE(s->config); i++)
			snd_soc_write(codec, WM8993_EQ1 + i, s->config[i]);

		snd_soc_update_bits(codec, WM8993_EQ1, WM8993_EQ_ENA, eq1);
	}

	return 0;
}
예제 #5
0
int main(void) {
	volatile unsigned int i;
	WDTCTL = WDTPW + WDTHOLD;		// Stop watchdog timer
	configure_clock();
	__delay_cycles(1000000);
	__delay_cycles(1000000);

	// Ready to Send
	//adf7021n_tx1010test();	// Ready to Receive
	// adf7021n_recvStart();
	//adf7021n_sendStart();
//	adf7021n_enable_data_interrupt();

	adf7021n_portSetup();



	// TX_XTAL = 19.2 MHz
	// fOUT = 437.525 MHz
	// fPFD = 3.84 MHz -> R = 5
	// fDev = 1000Hz
	// Data Rate = 1200bps


	// TX for RF Switch
//	P4DIR |= 0x04;
//	P4OUT |= 0x04;





//
//	// for Data Rate = 1200 bps
//	adf7021n_setDemodDivider(11);
//	adf7021n_setCDRDivider(45);




	// Power for PA ON
//	P4DIR |= 0x10;
//	P4OUT |= 0x10;
//

//	adf7021n_txCarriertest();










	while(1) {


//		volatile uint8_t i,j;
//
//		for (i = 0; i < 16; i++)
//		{
//
//			for (j= 0; j< 4 ; j++)
//			{
//				adf7021n_setVcoBias(i);
//						adf7021n_setVcoAdjust(j);
//					//	// 5dBm out
//					//	 adf7021n_setPowerAmp(ADF7021N_PA_RAMP_NO_RAMP, ADF7021N_PA_BIAS_9uA, 18);
//
//						// Best Power and Eff!!
//						adf7021n_setPowerAmp(ADF7021N_PA_RAMP_NO_RAMP, ADF7021N_PA_BIAS_9uA, 30);
//					//	adf7021n_setPowerAmp(ADF7021N_PA_RAMP_NO_RAMP, ADF7021N_PA_BIAS_9uA, 18);
//
//
//
//
//
//						P4DIR |= 0x10;
//						P4OUT |= 0x10;
//
//						adf7021n_setPowerAmpOn();
//
//
//					//	adf7021n_txEnable();
//					//	adf7021n_tx1010test();
//
//					//	_EINT();
//						adf7021n_txEnable();
//
//
//
//						adf7021n_txCarriertest();
//						__delay_cycles(1000000);
//							__delay_cycles(1000000);
//			}
//
//		}


//

		adf7021n_txInit();



		adf7021n_setRCounter(5);
		adf7021n_setIntegerN(227);
		adf7021n_setFracN(28772);
	// fDev = 1200 Hz at 300 bps
		adf7021n_setTxFreqDeviation(41);
		adf7021n_setDemodDivider(8);
		adf7021n_setCDRDivider(250);


	//  Best setting so far
		adf7021n_setVcoBias(7);
		adf7021n_setVcoAdjust(3);


		// Best Power and Eff!!
		// 5dBm out for current setting due to PA impedance mismatch
		adf7021n_setPowerAmp(ADF7021N_PA_RAMP_NO_RAMP, ADF7021N_PA_BIAS_9uA, 28); //Final tuning value!!!!

		adf7021n_setPowerAmpOn();
		adf7021n_txEnable();

		adf7021n_txCarriertest();
		__delay_cycles(1000000);
		__delay_cycles(1000000);
		__delay_cycles(1000000);
		__delay_cycles(1000000);
		__delay_cycles(1000000);
		__delay_cycles(1000000);
		__delay_cycles(1000000);

		adf7021n_txHightest();
		__delay_cycles(1000000);
		__delay_cycles(1000000);
		__delay_cycles(1000000);
		__delay_cycles(1000000);
		__delay_cycles(1000000);
		__delay_cycles(1000000);
		__delay_cycles(1000000);

		adf7021n_txLowtest();
		__delay_cycles(1000000);
		__delay_cycles(1000000);
		__delay_cycles(1000000);
		__delay_cycles(1000000);
		__delay_cycles(1000000);
		__delay_cycles(1000000);
		__delay_cycles(1000000);

		_EINT();

	 	ax25_makePacket(dstAddr, srcAddr, sendData, sizeof(sendData));
	 	P2IFG &= ~BIT3; // P2.3 IFG cleared just in case
	 	P2IE |= BIT3; // interrupt enable
		adf7021n_sendStart();
		for(i=0;i <80;i++)
	    __delay_cycles(1000000);

		P2IFG &= ~BIT3; // P2.3 IFG cleared just in case
		P2IE &= ~BIT3; // interrupt disable

     }
}