int op_lfork(t_vm *vm, t_process *process, int *params, int len)
{
t_process *fork;
unsigned char *addr;
addr = vm->memory + ((((short)params[0]) +
(process->next_instr - vm->memory)) % MEM_SIZE);
if (!(fork = new_process(addr, vm->current_cycle -
get_cycles_for_opcode(*process->next_instr))))
return (len);
if (!(fork->registres = copy_regs(process->registres)))
exit(1);
copy_state(fork, process);
ft_lstadd(&vm->processes, ft_lstnew(fork, sizeof(t_process)));
return (len);
}
int op_fork(t_vm *vm, t_process *process, int *params, int len)
{
t_process *fork;
unsigned char *addr;
addr = get_real_addr_of_ind(vm, process->next_instr, (short)params[0], 1);
if (!(fork = new_process(addr, vm->current_cycle -
get_cycles_for_opcode(*process->next_instr))))
return (len);
fork->carry = process->carry;
if (!(fork->registres = copy_regs(process->registres)))
exit(1);
fork->last_live = process->last_live;
fork->nb_live = process->nb_live;
fork->remaining_cycles = get_cycles_for_opcode(*fork->next_instr);
fork->current_opcode = *fork->next_instr;
if (fork->remaining_cycles > 0)
fork->remaining_cycles--;
ft_lstadd(&vm->processes, ft_lstnew(fork, sizeof(t_process)));
return (len);
}
/*-------------------------------------------------------------------*/
void ARCH_DEP(display_inst) (REGS *iregs, BYTE *inst)
{
QWORD qword; /* Doubleword work area */
BYTE opcode; /* Instruction operation code*/
int ilc; /* Instruction length */
#ifdef DISPLAY_INSTRUCTION_OPERANDS
int b1=-1, b2=-1, x1; /* Register numbers */
VADR addr1 = 0, addr2 = 0; /* Operand addresses */
#endif /*DISPLAY_INSTRUCTION_OPERANDS*/
char buf[256]; /* Message buffer */
int n; /* Number of bytes in buffer */
REGS *regs; /* Copied regs */
if (iregs->ghostregs)
regs = iregs;
else if ((regs = copy_regs(iregs)) == NULL)
return;
#if defined(_FEATURE_SIE)
if(SIE_MODE(regs))
logmsg(_("SIE: "));
#endif /*defined(_FEATURE_SIE)*/
#if 0
#if _GEN_ARCH == 370
logmsg("S/370 ");
#elif _GEN_ARCH == 390
logmsg("ESA/390 ");
#else
logmsg("Z/Arch ");
#endif
#endif
/* Display the PSW */
memset (qword, 0x00, sizeof(qword));
copy_psw (regs, qword);
if(sysblk.cpus>1)
{
n=sprintf(buf,"CPU%4.4X: ",regs->cpuad);
}
else
{
n=0;
}
n += sprintf (buf+n,
"PSW=%2.2X%2.2X%2.2X%2.2X %2.2X%2.2X%2.2X%2.2X ",
qword[0], qword[1], qword[2], qword[3],
qword[4], qword[5], qword[6], qword[7]);
#if defined(FEATURE_ESAME)
n += sprintf (buf + n,
"%2.2X%2.2X%2.2X%2.2X%2.2X%2.2X%2.2X%2.2X ",
qword[8], qword[9], qword[10], qword[11],
qword[12], qword[13], qword[14], qword[15]);
#endif /*defined(FEATURE_ESAME)*/
/* Exit if instruction is not valid */
if (inst == NULL)
{
logmsg (_("%sInstruction fetch error\n"), buf);
display_regs (regs);
if (!iregs->ghostregs) free(regs);
return;
}
/* Extract the opcode and determine the instruction length */
opcode = inst[0];
ilc = ILC(opcode);
/* Show registers associated with the instruction */
if (sysblk.showregsfirst)
display_inst_regs (regs, inst, opcode);
/* Display the instruction */
n += sprintf (buf+n, "INST=%2.2X%2.2X", inst[0], inst[1]);
if (ilc > 2) n += sprintf (buf+n, "%2.2X%2.2X", inst[2], inst[3]);
if (ilc > 4) n += sprintf (buf+n, "%2.2X%2.2X", inst[4], inst[5]);
logmsg ("%s %s", buf,(ilc<4) ? " " : (ilc<6) ? " " : "");
DISASM_INSTRUCTION(inst, buf);
logmsg("%s\n", buf);
#ifdef DISPLAY_INSTRUCTION_OPERANDS
/* Process the first storage operand */
if (ilc > 2
&& opcode != 0x84 && opcode != 0x85
&& opcode != 0xA5 && opcode != 0xA7
&& opcode != 0xB3
&& opcode != 0xC0 && opcode != 0xC4 && opcode != 0xC6
&& opcode != 0xEC)
{
/* Calculate the effective address of the first operand */
b1 = inst[2] >> 4;
addr1 = ((inst[2] & 0x0F) << 8) | inst[3];
if (b1 != 0)
{
addr1 += regs->GR(b1);
addr1 &= ADDRESS_MAXWRAP(regs);
}
/* Apply indexing for RX/RXE/RXF instructions */
if ((opcode >= 0x40 && opcode <= 0x7F) || opcode == 0xB1
|| opcode == 0xE3 || opcode == 0xED)
{
x1 = inst[1] & 0x0F;
if (x1 != 0)
{
addr1 += regs->GR(x1);
addr1 &= ADDRESS_MAXWRAP(regs);
}
}
}
