static inline void isr_common(uint8_t int_id) {
LPC_GPIO_PIN_INT->IST |= (1 << int_id);
isrctx[int_id].cb(isrctx[int_id].arg);
cortexm_isr_end();
}
static inline void irq_handler(uart_t uart)
{
#if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32L0) \
|| defined(CPU_FAM_STM32F3) || defined(CPU_FAM_STM32L4) \
|| defined(CPU_FAM_STM32F7)
uint32_t status = dev(uart)->ISR;
if (status & USART_ISR_RXNE) {
isr_ctx[uart].rx_cb(isr_ctx[uart].arg,
(uint8_t)dev(uart)->RDR & isr_ctx[uart].data_mask);
}
if (status & USART_ISR_ORE) {
dev(uart)->ICR |= USART_ICR_ORECF; /* simply clear flag on overrun */
}
#else
uint32_t status = dev(uart)->SR;
if (status & USART_SR_RXNE) {
isr_ctx[uart].rx_cb(isr_ctx[uart].arg,
(uint8_t)dev(uart)->DR & isr_ctx[uart].data_mask);
}
if (status & USART_SR_ORE) {
/* ORE is cleared by reading SR and DR sequentially */
dev(uart)->DR;
}
#endif
cortexm_isr_end();
}
static inline void rx_irq(int dev)
{
if (_uart(dev)->IF & USART_IF_RXDATAV) {
uint8_t data = (uint8_t)_uart(dev)->RXDATA;
isr_ctx[dev].rx_cb(isr_ctx[dev].arg, data);
}
cortexm_isr_end();
}
static inline void isr_handler(int num)
{
Uart *dev = uart_config[num].dev;
if (dev->UART_SR & UART_SR_RXRDY) {
ctx[num].rx_cb(ctx[num].arg, (uint8_t)dev->UART_RHR);
}
cortexm_isr_end();
}
/**
* @brief Actual interrupt handler for both even and odd pin index numbers.
*/
static void gpio_irq(void)
{
for (int i = 0; i < NUMOF_IRQS; i++) {
if (GPIO_IntGet() & (1 << i)) {
isr_ctx[i].cb(isr_ctx[i].arg);
GPIO_IntClear(1 << i);
}
}
cortexm_isr_end();
}
void isr_i2c(void)
{
/* Clear the interrupt flag */
I2CM_ICR = 1;
/* Unlock the wait mutex */
mutex_unlock(&i2c_wait_mutex);
cortexm_isr_end();
}
/**
* @brief handle interrupt for a timer
*
* @param[in] tim index of the timer
*/
static inline void isr_handler(tim_t tim)
{
uint32_t mis = dev(tim)->MIS;
dev(tim)->ICLR = mis;
if (mis & GPT_IMR_TAMIM) {
dev(tim)->IMR &= ~GPT_IMR_TAMIM;
ctx[tim].cb(ctx[tim].arg, 0);
}
cortexm_isr_end();
}
static inline void irq_handler_transfer(SPI_TypeDef *spi, spi_t dev)
{
if (spi->SR & SPI_SR_RXNE) {
char data;
data = spi->DR;
data = spi_config[dev].cb(data);
spi->DR = data;
}
/* see if a thread with higher priority wants to run now */
cortexm_isr_end();
}
void TIMER_0_ISR(void)
{
TIMER_TypeDef *tim = timer_config[0].timer;
for (int i = 0; i < CC_CHANNELS; i++) {
if (tim->IF & (TIMER_IF_CC0 << i)) {
tim->CC[i].CTRL = _TIMER_CC_CTRL_MODE_OFF;
tim->IFC = (TIMER_IFC_CC0 << i);
isr_ctx[0].cb(isr_ctx[0].arg, i);
}
}
cortexm_isr_end();
}
static inline void isr_handler(tim_t tim)
{
uint32_t status = dev(tim)->TC_CHANNEL[0].TC_SR;
for (int i = 0; i < TIMER_CHANNELS; i++) {
if (status & (TC_SR_CPAS << i)) {
dev(tim)->TC_CHANNEL[0].TC_IDR = (TC_IDR_CPAS << i);
isr_ctx[tim].cb(isr_ctx[tim].arg, i);
}
}
cortexm_isr_end();
}
static inline void irq_handler(uint8_t uartnum, SercomUsart *dev)
{
if (dev->INTFLAG.bit.RXC) {
/* cleared by reading DATA regiser */
uint8_t data = (uint8_t)dev->DATA.reg;
uart_config[uartnum].rx_cb(uart_config[uartnum].arg, data);
}
else if (dev->INTFLAG.bit.ERROR) {
/* clear error flag */
dev->INTFLAG.reg |= SERCOM_USART_INTFLAG_ERROR;
}
cortexm_isr_end();
}
static inline void irq_handler(int dev)
{
SercomUsart *uart = _uart(dev);
if (uart->INTFLAG.reg & SERCOM_USART_INTFLAG_RXC) {
/* interrupt flag is cleared by reading the data register */
uart_ctx[dev].rx_cb(uart_ctx[dev].arg, (uint8_t)(uart->DATA.reg));
}
else if (uart->INTFLAG.reg & SERCOM_USART_INTFLAG_ERROR) {
/* clear error flag */
uart->INTFLAG.reg = SERCOM_USART_INTFLAG_ERROR;
}
cortexm_isr_end();
}
static inline void irq_handler(int num)
{
for (unsigned i = 0; i < timer_config[num].channels; i++) {
if (dev(num)->EVENTS_COMPARE[i] == 1) {
dev(num)->EVENTS_COMPARE[i] = 0;
if (ctx[num].flags & (1 << i)) {
ctx[num].flags &= ~(1 << i);
dev(num)->INTENCLR = (TIMER_INTENSET_COMPARE0_Msk << i);
ctx[num].cb(ctx[num].arg, i);
}
}
}
cortexm_isr_end();
}
static inline void handle_isr(uint8_t port_num)
{
cc2538_gpio_t *port = ((cc2538_gpio_t *)GPIO_BASE) + port_num;
uint32_t state = port->MIS;
port->IC = 0x000000ff;
port->IRQ_DETECT_ACK = (0xff << (port_num * GPIO_BITS_PER_PORT));
for (int i = 0; i < GPIO_BITS_PER_PORT; i++) {
if (state & (1 << i)) {
isr_ctx[port_num][i].cb(isr_ctx[port_num][i].arg);
}
}
cortexm_isr_end();
}
static inline void irq_handler_transfer(SPI_Type *spi, spi_t dev)
{
if (spi->SR & SPI_SR_RFDF_MASK) {
char data;
data = (char)spi->POPR;
data = spi_config[dev].cb(data);
spi->PUSHR = SPI_PUSHR_CTAS(0)
| SPI_PUSHR_EOQ_MASK
| SPI_PUSHR_TXDATA(data);
}
/* see if a thread with higher priority wants to run now */
cortexm_isr_end();
}
void isr_rtc(void)
{
if (RTC->MODE2.INTFLAG.bit.ALARM0) {
rtc_callback.cb(rtc_callback.arg);
/* clear flag */
RTC->MODE2.INTFLAG.reg |= RTC_MODE2_INTFLAG_ALARM0;
}
if (RTC->MODE2.INTFLAG.bit.OVF) {
/* clear flag */
RTC->MODE2.INTFLAG.reg |= RTC_MODE2_INTFLAG_OVF;
/* At 1Hz, RTC goes till 63 years (2^5, see 17.8.22 in datasheet)
* Start RTC again with reference_year 64 years more (Be careful with alarm set) */
reference_year += 64;
}
cortexm_isr_end();
}
void isr_rtc(void)
{
RtcMode2 *rtcMode2 = &(RTC_DEV);
uint16_t status = rtcMode2->INTFLAG.reg;
if ((status & RTC_MODE2_INTFLAG_ALARM0) && (rtc_callback.cb != NULL)) {
rtc_callback.cb(rtc_callback.arg);
rtcMode2->INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM0;
}
if (status & RTC_MODE2_INTFLAG_OVF) {
/* At 1Hz, RTC goes till 63 years (2^5, see 17.8.22 in datasheet)
* Start RTC again with reference_year 64 years more (Be careful with alarm set) */
reference_year += 64;
rtcMode2->INTFLAG.reg = RTC_MODE2_INTFLAG_OVF;
}
cortexm_isr_end();
}
void RTT_ISR(void)
{
RtcMode0 *rtcMode0 = &(RTT_DEV);
uint8_t status = rtcMode0->INTFLAG.reg;
if ( (status & RTC_MODE0_INTFLAG_CMP0) && (rtt_callback.alarm_cb != NULL) ) {
rtt_callback.alarm_cb(rtt_callback.alarm_arg);
rtcMode0->INTFLAG.reg |= RTC_MODE0_INTFLAG_CMP0;
}
if ( (status & RTC_MODE0_INTFLAG_OVF) && (rtt_callback.overflow_cb != NULL) ) {
rtt_callback.overflow_cb(rtt_callback.overflow_arg);
rtcMode0->INTFLAG.reg |= RTC_MODE0_INTFLAG_OVF;
}
cortexm_isr_end();
}
static inline void lptmr_irq_handler(tim_t tim)
{
uint8_t dev = _lptmr_index(tim);
LPTMR_Type *hw = lptmr_config[dev].dev;
lptmr[dev].running = 0;
/* Disable interrupt generation, keep timer running */
/* Do not clear TCF flag here, it is required for writing CMR without
* disabling timer first */
hw->CSR = LPTMR_CSR_TEN_MASK | LPTMR_CSR_TFC_MASK;
if (lptmr[dev].isr_ctx.cb != NULL) {
lptmr[dev].isr_ctx.cb(lptmr[dev].isr_ctx.arg, 0);
}
cortexm_isr_end();
}
static void _isr_gpio(uint32_t port_num){
const uint32_t port_addr = _port_base[port_num];
uint32_t isr = ROM_GPIOPinIntStatus(port_addr, true);
uint8_t i;
for (i=0; i<8; i++, isr>>=1) {
if ((isr & 0x1) == 0){
continue;
}
ROM_GPIOPinIntClear(port_addr, 1 << i);
if (gpio_config[port_num][i].cb){
gpio_config[port_num][i].cb(gpio_config[port_num][i].arg);
}
}
cortexm_isr_end();
}
void TIMER_0_ISR(void)
{
if (TIMER_0_DEV.INTFLAG.bit.MC0 && TIMER_0_DEV.INTENSET.bit.MC0) {
if(config[TIMER_0].cb) {
TIMER_0_DEV.INTFLAG.reg |= TC_INTFLAG_MC0;
TIMER_0_DEV.INTENCLR.reg = TC_INTENCLR_MC0;
config[TIMER_0].cb(config[TIMER_0].arg, 0);
}
}
else if (TIMER_0_DEV.INTFLAG.bit.MC1 && TIMER_0_DEV.INTENSET.bit.MC1) {
if(config[TIMER_0].cb) {
TIMER_0_DEV.INTFLAG.reg |= TC_INTFLAG_MC1;
TIMER_0_DEV.INTENCLR.reg = TC_INTENCLR_MC1;
config[TIMER_0].cb(config[TIMER_0].arg, 1);
}
}
cortexm_isr_end();
}
void isr_lptim1(void)
{
if (LPTIM1->ISR & LPTIM_ISR_CMPM) {
if (to_cb) {
/* 'consume' the callback (as it might be set again in the cb) */
rtt_cb_t tmp = to_cb;
to_cb = NULL;
tmp(to_arg);
}
}
if (LPTIM1->ISR & LPTIM_ISR_ARRM) {
if (ovf_cb) {
ovf_cb(ovf_arg);
}
}
LPTIM1->ICR = (LPTIM_ICR_ARRMCF | LPTIM_ICR_CMPMCF);
cortexm_isr_end();
}
void UART_1_ISR(void)
{
uint_fast16_t mis;
/* Latch the Masked Interrupt Status and clear any active flags */
mis = UART_1_DEV->cc2538_uart_mis.MIS;
UART_1_DEV->ICR = mis;
while (UART_1_DEV->cc2538_uart_fr.FRbits.RXFE == 0) {
uart_config[1].rx_cb(uart_config[1].arg, UART_1_DEV->DR);
}
if (mis & (OEMIS | BEMIS | FEMIS)) {
/* ISR triggered due to some error condition */
reset(UART_1_DEV);
}
cortexm_isr_end();
}
void RTT_ISR(void)
{
RTC_Type *rtt = RTT_DEV;
if (rtt->SR & RTC_SR_TAF_MASK) {
if (rtt_callback.alarm_cb != NULL) {
/* Disable Timer Alarm Interrupt */
rtt->IER &= ~RTC_IER_TAIE_MASK;
rtt_callback.alarm_cb(rtt_callback.alarm_arg);
}
}
if (rtt->SR & RTC_SR_TOF_MASK) {
if (rtt_callback.overflow_cb != NULL) {
rtt_callback.overflow_cb(rtt_callback.overflow_arg);
}
}
cortexm_isr_end();
}
/** @brief Interrupt service routine for Port D */
void isr_gpiod(void)
{
int mis, bit;
gpio_isr_ctx_t* state;
/* Latch and clear the interrupt status early on: */
mis = GPIO_D->MIS;
GPIO_D->IC = 0x000000ff;
GPIO_D->IRQ_DETECT_ACK = 0xff000000;
for (bit = 0; bit < GPIO_BITS_PER_PORT; bit++) {
if (mis & 1) {
state = gpio_config + reverse_pin_lut[GPIO_PXX_TO_NUM(PORT_D, bit)];
state->cb(state->arg);
}
mis >>= 1;
}
cortexm_isr_end();
}
/**
* @brief timer interrupt handler
*
* @param[in] num GPT instance number
* @param[in] chn channel number (0=A, 1=B)
*/
static void irq_handler(tim_t tim, int channel)
{
DEBUG("%s(%u,%d)\n", __FUNCTION__, tim, channel);
assert(tim < TIMER_NUMOF);
assert(channel < (int)timer_config[tim].chn);
uint32_t mis;
/* Latch the active interrupt flags */
mis = dev(tim)->MIS & chn_isr_cfg[channel].mask;
/* Clear the latched interrupt flags */
dev(tim)->ICR = mis;
if (mis & chn_isr_cfg[channel].flag) {
/* Disable further match interrupts for this timer/channel */
dev(tim)->IMR &= ~chn_isr_cfg[channel].flag;
/* Invoke the callback function */
isr_ctx[tim].cb(isr_ctx[tim].arg, channel);
}
cortexm_isr_end();
}
static void irq_handler_b(int n) {
uint32_t mis;
/* Latch the active interrupt flags */
mis = GPTIMER[n].MIS & TIMER_B_IRQ_MASK;
/* Clear the latched interrupt flags */
GPTIMER[n].ICR = mis;
if (mis & TBMIM) {
/* This is a Timer B Match Interrupt */
/* Disable further match interrupts for this timer/channel */
GPTIMER[n].cc2538_gptimer_imr.IMR &= ~TBMIM;
/* Invoke the callback function */
assert(config[n].cb != NULL);
config[n].cb(config[n].arg, 1);
}
cortexm_isr_end();
}
/**
* @brief Radio interrupt routine
*/
void isr_radio(void)
{
if (NRF_RADIO->EVENTS_END == 1) {
NRF_RADIO->EVENTS_END = 0;
/* did we just send or receive something? */
if (state == STATE_RX) {
/* drop packet on invalid CRC */
if ((NRF_RADIO->CRCSTATUS != 1) || !(nrfmin_dev.event_callback)) {
rx_buf.pkt.hdr.len = 0;
NRF_RADIO->TASKS_START = 1;
return;
}
rx_lock = 0;
nrfmin_dev.event_callback(&nrfmin_dev, NETDEV_EVENT_ISR);
}
else if (state == STATE_TX) {
goto_target_state();
}
}
cortexm_isr_end();
}
static inline void pit_irq_handler(tim_t dev)
{
uint8_t ch = pit_config[_pit_index(dev)].count_ch;
pit_t *pit_ctx = &pit[_pit_index(dev)];
if (!PIT->CHANNEL[ch].TFLG) {
DEBUG("PIT%u!TFLG\n", (unsigned)dev);
return;
}
/* Add the overflow amount to the counter before resetting */
/* (this may be > 0 if the IRQ handler was delayed e.g. by irq_disable etc.) */
pit_ctx->count += PIT->CHANNEL[ch].LDVAL - PIT->CHANNEL[ch].CVAL;
/* inline pit_clear */
PIT->CHANNEL[ch].TCTRL = 0;
PIT->CHANNEL[ch].LDVAL = PIT_MAX_VALUE;
PIT->CHANNEL[ch].TFLG = PIT_TFLG_TIF_MASK;
PIT->CHANNEL[ch].TCTRL = PIT_TCTRL_CHN_MASK | PIT_TCTRL_TEN_MASK;
if (pit_ctx->isr_ctx.cb != NULL) {
pit_ctx->isr_ctx.cb(pit_ctx->isr_ctx.arg, 0);
}
cortexm_isr_end();
}
void TIMER_0_ISR(void)
{
if (TIMER_0_DEV->IR & MR0_FLAG) {
TIMER_0_DEV->IR |= (MR0_FLAG);
TIMER_0_DEV->MCR &= ~(1 << 0);
config[TIMER_0].cb(config[TIMER_0].arg, 0);
}
if (TIMER_0_DEV->IR & MR1_FLAG) {
TIMER_0_DEV->IR |= (MR1_FLAG);
TIMER_0_DEV->MCR &= ~(1 << 3);
config[TIMER_0].cb(config[TIMER_0].arg, 1);
}
if (TIMER_0_DEV->IR & MR2_FLAG) {
TIMER_0_DEV->IR |= (MR2_FLAG);
TIMER_0_DEV->MCR &= ~(1 << 6);
config[TIMER_0].cb(config[TIMER_0].arg, 2);
}
if (TIMER_0_DEV->IR & MR3_FLAG) {
TIMER_0_DEV->IR |= (MR3_FLAG);
TIMER_0_DEV->MCR &= ~(1 << 9);
config[TIMER_0].cb(config[TIMER_0].arg, 3);
}
cortexm_isr_end();
}
