static void key_handler(enum cpcap_irqs irq, void *data)
{
struct cpcap_3mm5_data *data_3mm5 = data;
if ((irq != CPCAP_IRQ_MB2) && (irq != CPCAP_IRQ_UC_PRIMACRO_5))
return;
if ((cpcap_irq_sense(data_3mm5->cpcap, CPCAP_IRQ_HS, 1) == 1) ||
(switch_get_state(&data_3mm5->sdev) != HEADSET_WITH_MIC)) {
hs_handler(CPCAP_IRQ_HS, data_3mm5);
return;
}
if ((cpcap_irq_sense(data_3mm5->cpcap, CPCAP_IRQ_MB2, 0) == 0) ||
(cpcap_irq_sense(data_3mm5->cpcap, CPCAP_IRQ_PTT, 0) == 0)) {
send_key_event(data_3mm5, 1);
/* If macro not available, only short presses are supported */
if (!cpcap_uc_status(data_3mm5->cpcap, CPCAP_MACRO_5)) {
send_key_event(data_3mm5, 0);
/* Attempt to restart the macro for next time. */
cpcap_uc_start(data_3mm5->cpcap, CPCAP_MACRO_5);
}
} else
send_key_event(data_3mm5, 0);
cpcap_irq_unmask(data_3mm5->cpcap, CPCAP_IRQ_MB2);
cpcap_irq_unmask(data_3mm5->cpcap, CPCAP_IRQ_UC_PRIMACRO_5);
}
static void hs_handler(enum cpcap_irqs irq, void *data)
{
struct cpcap_3mm5_data *data_3mm5 = data;
int new_state = NO_DEVICE;
if (irq != CPCAP_IRQ_HS)
return;
/* HS sense of 1 means no headset present, 0 means headset attached. */
if (cpcap_irq_sense(data_3mm5->cpcap, CPCAP_IRQ_HS, 1) == 1) {
cpcap_regacc_write(data_3mm5->cpcap, CPCAP_REG_TXI, 0,
(CPCAP_BIT_MB_ON2 | CPCAP_BIT_PTT_CMP_EN));
cpcap_regacc_write(data_3mm5->cpcap, CPCAP_REG_RXOA, 0,
CPCAP_BIT_ST_HS_CP_EN);
audio_low_power_set(data_3mm5, &data_3mm5->audio_low_pwr_det);
cpcap_irq_mask(data_3mm5->cpcap, CPCAP_IRQ_MB2);
cpcap_irq_mask(data_3mm5->cpcap, CPCAP_IRQ_UC_PRIMACRO_5);
cpcap_irq_clear(data_3mm5->cpcap, CPCAP_IRQ_MB2);
cpcap_irq_clear(data_3mm5->cpcap, CPCAP_IRQ_UC_PRIMACRO_5);
cpcap_irq_unmask(data_3mm5->cpcap, CPCAP_IRQ_HS);
send_key_event(data_3mm5, 0);
/* Config mux switch to accy detection. */
cpcap_regacc_write(data_3mm5->cpcap, CPCAP_REG_GPIO2, 0,
CPCAP_BIT_GPIO2DRV);
cpcap_regacc_write(data_3mm5->cpcap, CPCAP_REG_GPIO4, 0,
CPCAP_BIT_GPIO4DRV);
cpcap_uc_stop(data_3mm5->cpcap, CPCAP_MACRO_5);
} else {
/* Config mux switch to pass headset mic. */
cpcap_regacc_write(data_3mm5->cpcap, CPCAP_REG_GPIO2, 0,
CPCAP_BIT_GPIO2DRV);
cpcap_regacc_write(data_3mm5->cpcap, CPCAP_REG_GPIO4,
CPCAP_BIT_GPIO4DRV, CPCAP_BIT_GPIO4DRV);
cpcap_regacc_write(data_3mm5->cpcap, CPCAP_REG_TXI,
(CPCAP_BIT_MB_ON2 | CPCAP_BIT_PTT_CMP_EN),
(CPCAP_BIT_MB_ON2 | CPCAP_BIT_PTT_CMP_EN));
cpcap_regacc_write(data_3mm5->cpcap, CPCAP_REG_RXOA,
CPCAP_BIT_ST_HS_CP_EN,
CPCAP_BIT_ST_HS_CP_EN);
audio_low_power_clear(data_3mm5, &data_3mm5->audio_low_pwr_det);
/* Give PTTS time to settle 10ms */
msleep(11);
if (cpcap_irq_sense(data_3mm5->cpcap, CPCAP_IRQ_PTT, 1) <= 0) {
/* Headset without mic and MFB is detected. (May also
* be a headset with the MFB pressed.) */
new_state = HEADSET_WITHOUT_MIC;
} else {
new_state = HEADSET_WITH_MIC;
/* Config mux switch to pass headset mic. */
cpcap_regacc_write(data_3mm5->cpcap, CPCAP_REG_GPIO2, 0,
CPCAP_BIT_GPIO2DRV);
cpcap_regacc_write(data_3mm5->cpcap, CPCAP_REG_GPIO4,
CPCAP_BIT_GPIO4DRV, CPCAP_BIT_GPIO4DRV);
}
cpcap_irq_clear(data_3mm5->cpcap, CPCAP_IRQ_MB2);
cpcap_irq_clear(data_3mm5->cpcap, CPCAP_IRQ_UC_PRIMACRO_5);
cpcap_irq_unmask(data_3mm5->cpcap, CPCAP_IRQ_HS);
cpcap_irq_unmask(data_3mm5->cpcap, CPCAP_IRQ_MB2);
cpcap_irq_unmask(data_3mm5->cpcap, CPCAP_IRQ_UC_PRIMACRO_5);
cpcap_uc_start(data_3mm5->cpcap, CPCAP_MACRO_5);
headset_in_stamp = jiffies;
}
switch_set_state(&data_3mm5->sdev, new_state);
if (data_3mm5->cpcap->h2w_new_state)
data_3mm5->cpcap->h2w_new_state(new_state);
dev_info(&data_3mm5->cpcap->spi->dev, "New headset state: %d\n",
new_state);
}
static void hs_handler(enum cpcap_irqs irq, void *data)
{
struct cpcap_3mm5_data *data_3mm5 = data;
int new_state = NO_DEVICE;
if (irq != CPCAP_IRQ_HS)
return;
/* HS sense of 1 means no headset present, 0 means headset attached. */
if (cpcap_irq_sense(data_3mm5->cpcap, CPCAP_IRQ_HS, 1) == 1) {
cpcap_regacc_write(data_3mm5->cpcap, CPCAP_REG_TXI, 0,
(CPCAP_BIT_MB_ON2 | CPCAP_BIT_PTT_CMP_EN));
cpcap_regacc_write(data_3mm5->cpcap, CPCAP_REG_RXOA, 0,
CPCAP_BIT_ST_HS_CP_EN);
audio_low_power_set(data_3mm5, &data_3mm5->audio_low_pwr_det);
cpcap_irq_mask(data_3mm5->cpcap, CPCAP_IRQ_MB2);
cpcap_irq_mask(data_3mm5->cpcap, CPCAP_IRQ_UC_PRIMACRO_5);
cpcap_irq_clear(data_3mm5->cpcap, CPCAP_IRQ_MB2);
cpcap_irq_clear(data_3mm5->cpcap, CPCAP_IRQ_UC_PRIMACRO_5);
cpcap_irq_unmask(data_3mm5->cpcap, CPCAP_IRQ_HS);
send_key_event(data_3mm5, 0);
data_3mm5->unsupported_headset=0;
cpcap_uc_stop(data_3mm5->cpcap, CPCAP_BANK_PRIMARY, CPCAP_MACRO_5);
} else {
cpcap_regacc_write(data_3mm5->cpcap, CPCAP_REG_TXI,
(CPCAP_BIT_MB_ON2 | CPCAP_BIT_PTT_CMP_EN),
(CPCAP_BIT_MB_ON2 | CPCAP_BIT_PTT_CMP_EN));
cpcap_regacc_write(data_3mm5->cpcap, CPCAP_REG_RXOA,
CPCAP_BIT_ST_HS_CP_EN,
CPCAP_BIT_ST_HS_CP_EN);
audio_low_power_clear(data_3mm5, &data_3mm5->audio_low_pwr_det);
/* Give PTTS time to settle */
mdelay(2);
if (cpcap_irq_sense(data_3mm5->cpcap, CPCAP_IRQ_PTT, 1) <= 0) {
/* Headset without mic and MFB is detected. (May also
* be a headset with the MFB pressed.) */
new_state = HEADSET_WITHOUT_MIC;
} else {
if(cpcap_irq_sense(data_3mm5->cpcap, CPCAP_IRQ_MB2, 1) == 0) {
/*cvk011c: This is an Apple HS and its microphone will not work with CPCAP due to HW problem.
Detect it as HS without mic to avoid problems with HS BTN detection and MIC audio */
new_state = HEADSET_WITHOUT_MIC;
dev_info(&data_3mm5->cpcap->spi->dev, "Unsupported headset detected\n");
data_3mm5->unsupported_headset=1;
}else
new_state = HEADSET_WITH_MIC;
}
cpcap_irq_clear(data_3mm5->cpcap, CPCAP_IRQ_MB2);
cpcap_irq_clear(data_3mm5->cpcap, CPCAP_IRQ_UC_PRIMACRO_5);
cpcap_irq_unmask(data_3mm5->cpcap, CPCAP_IRQ_HS);
cpcap_irq_unmask(data_3mm5->cpcap, CPCAP_IRQ_MB2);
cpcap_irq_unmask(data_3mm5->cpcap, CPCAP_IRQ_UC_PRIMACRO_5);
cpcap_uc_start(data_3mm5->cpcap, CPCAP_BANK_PRIMARY, CPCAP_MACRO_5);
}
switch_set_state(&data_3mm5->sdev, new_state);
if (data_3mm5->cpcap->h2w_new_state)
data_3mm5->cpcap->h2w_new_state(new_state);
dev_info(&data_3mm5->cpcap->spi->dev, "New headset state: %d\n",
new_state);
}