__init void cpu_probe(void)
{
struct cpuinfo_mips *c = ¤t_cpu_data;
c->processor_id = PRID_IMP_UNKNOWN;
c->fpu_id = FPIR_IMP_NONE;
c->cputype = CPU_UNKNOWN;
/* add by rupert*/
c->cputype = CPU_R3000;
c->isa_level = MIPS_CPU_ISA_I;
c->options = MIPS_CPU_TLB;
c->tlbsize = 16;
return;
c->processor_id = read_c0_prid();
switch (c->processor_id & 0xff0000) {
case PRID_COMP_LEGACY:
cpu_probe_legacy(c);
break;
case PRID_COMP_MIPS:
cpu_probe_mips(c);
break;
case PRID_COMP_ALCHEMY:
cpu_probe_alchemy(c);
break;
case PRID_COMP_SIBYTE:
cpu_probe_sibyte(c);
break;
case PRID_COMP_SANDCRAFT:
cpu_probe_sandcraft(c);
break;
default:
c->cputype = CPU_UNKNOWN;
}
if (c->options & MIPS_CPU_FPU)
c->fpu_id = cpu_get_fpu_id();
}
__init void cpu_probe(void)
{
struct cpuinfo_mips *c = ¤t_cpu_data;
c->processor_id = PRID_IMP_UNKNOWN;
c->fpu_id = FPIR_IMP_NONE;
c->cputype = CPU_UNKNOWN;
c->processor_id = read_c0_prid();
switch (c->processor_id & 0xff0000) {
case PRID_COMP_LEGACY:
cpu_probe_legacy(c);
break;
case PRID_COMP_MIPS:
cpu_probe_mips(c);
break;
case PRID_COMP_ALCHEMY:
cpu_probe_alchemy(c);
break;
case PRID_COMP_SIBYTE:
cpu_probe_sibyte(c);
break;
#if defined(CONFIG_MIPS_BRCM)
case PRID_COMP_BROADCOM:
cpu_probe_broadcom(c);
break;
#endif
case PRID_COMP_SANDCRAFT:
cpu_probe_sandcraft(c);
break;
default:
c->cputype = CPU_UNKNOWN;
}
if (c->options & MIPS_CPU_FPU)
c->fpu_id = cpu_get_fpu_id();
}
/*
* Check the CPU has an FPU the official way.
*/
static inline int __cpu_has_fpu(void)
{
return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE);
}
static inline void cpu_probe(void)
{
#ifdef CONFIG_CPU_MIPS32
unsigned long config0 = read_32bit_cp0_register(CP0_CONFIG);
unsigned long config1;
if (config0 & (1 << 31)) {
/* MIPS32 compliant CPU. Read Config 1 register. */
mips_cpu.isa_level = MIPS_CPU_ISA_M32;
mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
MIPS_CPU_4KTLB | MIPS_CPU_COUNTER | MIPS_CPU_DIVEC;
config1 = read_mips32_cp0_config1();
if (config1 & (1 << 3))
mips_cpu.options |= MIPS_CPU_WATCH;
if (config1 & (1 << 2))
mips_cpu.options |= MIPS_CPU_MIPS16;
if (config1 & (1 << 1))
mips_cpu.options |= MIPS_CPU_EJTAG;
if (config1 & 1)
mips_cpu.options |= MIPS_CPU_FPU;
mips_cpu.scache.flags = MIPS_CACHE_NOT_PRESENT;
}
#endif
mips_cpu.processor_id = read_32bit_cp0_register(CP0_PRID);
switch (mips_cpu.processor_id & 0xff0000) {
case PRID_COMP_LEGACY:
switch (mips_cpu.processor_id & 0xff00) {
case PRID_IMP_R2000:
mips_cpu.cputype = CPU_R2000;
mips_cpu.isa_level = MIPS_CPU_ISA_I;
mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_NOFPUEX;
if (cpu_has_fpu())
mips_cpu.options |= MIPS_CPU_FPU;
mips_cpu.tlbsize = 64;
break;
case PRID_IMP_R3000:
if ((mips_cpu.processor_id & 0xff) == PRID_REV_R3000A)
if (cpu_has_confreg())
mips_cpu.cputype = CPU_R3081E;
else
mips_cpu.cputype = CPU_R3000A;
else
mips_cpu.cputype = CPU_R3000;
mips_cpu.isa_level = MIPS_CPU_ISA_I;
mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_NOFPUEX;
if (cpu_has_fpu())
mips_cpu.options |= MIPS_CPU_FPU;
mips_cpu.tlbsize = 64;
break;
case PRID_IMP_R4000:
if ((mips_cpu.processor_id & 0xff) == PRID_REV_R4400)
mips_cpu.cputype = CPU_R4400SC;
else
mips_cpu.cputype = CPU_R4000SC;
mips_cpu.isa_level = MIPS_CPU_ISA_III;
mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU |
MIPS_CPU_32FPR | MIPS_CPU_WATCH |
MIPS_CPU_VCE;
mips_cpu.tlbsize = 48;
break;
case PRID_IMP_VR41XX:
mips_cpu.cputype = CPU_VR41XX;
mips_cpu.isa_level = MIPS_CPU_ISA_III;
mips_cpu.options = R4K_OPTS;
mips_cpu.tlbsize = 32;
break;
case PRID_IMP_R4300:
mips_cpu.cputype = CPU_R4300;
mips_cpu.isa_level = MIPS_CPU_ISA_III;
mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU |
MIPS_CPU_32FPR;
mips_cpu.tlbsize = 32;
break;
case PRID_IMP_R4600:
mips_cpu.cputype = CPU_R4600;
mips_cpu.isa_level = MIPS_CPU_ISA_III;
mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU;
mips_cpu.tlbsize = 48;
break;
#if 0
case PRID_IMP_R4650:
/*
* This processor doesn't have an MMU, so it's not
* "real easy" to run Linux on it. It is left purely
* for documentation. Commented out because it shares
* it's c0_prid id number with the TX3900.
*/
mips_cpu.cputype = CPU_R4650;
mips_cpu.isa_level = MIPS_CPU_ISA_III;
mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU;
mips_cpu.tlbsize = 48;
break;
#endif
case PRID_IMP_TX39:
mips_cpu.isa_level = MIPS_CPU_ISA_I;
mips_cpu.options = MIPS_CPU_TLB;
if ((mips_cpu.processor_id & 0xf0) ==
(PRID_REV_TX3927 & 0xf0)) {
mips_cpu.cputype = CPU_TX3927;
mips_cpu.tlbsize = 64;
mips_cpu.icache.ways = 2;
mips_cpu.dcache.ways = 2;
} else {
switch (mips_cpu.processor_id & 0xff) {
case PRID_REV_TX3912:
mips_cpu.cputype = CPU_TX3912;
mips_cpu.tlbsize = 32;
break;
case PRID_REV_TX3922:
mips_cpu.cputype = CPU_TX3922;
mips_cpu.tlbsize = 64;
break;
default:
mips_cpu.cputype = CPU_UNKNOWN;
break;
}
}
break;
case PRID_IMP_R4700:
mips_cpu.cputype = CPU_R4700;
mips_cpu.isa_level = MIPS_CPU_ISA_III;
mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU |
MIPS_CPU_32FPR;
mips_cpu.tlbsize = 48;
break;
case PRID_IMP_TX49:
mips_cpu.cputype = CPU_TX49XX;
mips_cpu.isa_level = MIPS_CPU_ISA_III;
mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU |
MIPS_CPU_32FPR;
mips_cpu.tlbsize = 48;
mips_cpu.icache.ways = 4;
mips_cpu.dcache.ways = 4;
break;
case PRID_IMP_R5000:
mips_cpu.cputype = CPU_R5000;
mips_cpu.isa_level = MIPS_CPU_ISA_IV;
mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU |
MIPS_CPU_32FPR;
mips_cpu.tlbsize = 48;
break;
case PRID_IMP_R5432:
mips_cpu.cputype = CPU_R5432;
mips_cpu.isa_level = MIPS_CPU_ISA_IV;
mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU |
MIPS_CPU_32FPR | MIPS_CPU_WATCH;
mips_cpu.tlbsize = 48;
break;
case PRID_IMP_R5500:
mips_cpu.cputype = CPU_R5500;
mips_cpu.isa_level = MIPS_CPU_ISA_IV;
mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU |
MIPS_CPU_32FPR | MIPS_CPU_WATCH;
mips_cpu.tlbsize = 48;
break;
case PRID_IMP_NEVADA:
mips_cpu.cputype = CPU_NEVADA;
mips_cpu.isa_level = MIPS_CPU_ISA_IV;
mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU |
MIPS_CPU_32FPR | MIPS_CPU_DIVEC;
mips_cpu.tlbsize = 48;
mips_cpu.icache.ways = 2;
mips_cpu.dcache.ways = 2;
break;
case PRID_IMP_R6000:
mips_cpu.cputype = CPU_R6000;
mips_cpu.isa_level = MIPS_CPU_ISA_II;
mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_FPU;
mips_cpu.tlbsize = 32;
break;
case PRID_IMP_R6000A:
mips_cpu.cputype = CPU_R6000A;
mips_cpu.isa_level = MIPS_CPU_ISA_II;
mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_FPU;
mips_cpu.tlbsize = 32;
break;
case PRID_IMP_RM7000:
mips_cpu.cputype = CPU_RM7000;
mips_cpu.isa_level = MIPS_CPU_ISA_IV;
mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU |
MIPS_CPU_32FPR;
/*
* Undocumented RM7000: Bit 29 in the info register of
* the RM7000 v2.0 indicates if the TLB has 48 or 64
* entries.
*
* 29 1 => 64 entry JTLB
* 0 => 48 entry JTLB
*/
mips_cpu.tlbsize = (get_info() & (1 << 29)) ? 64 : 48;
break;
case PRID_IMP_R8000:
mips_cpu.cputype = CPU_R8000;
mips_cpu.isa_level = MIPS_CPU_ISA_IV;
mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
MIPS_CPU_FPU | MIPS_CPU_32FPR;
mips_cpu.tlbsize = 384; /* has wierd TLB: 3-way x 128 */
break;
case PRID_IMP_R10000:
mips_cpu.cputype = CPU_R10000;
mips_cpu.isa_level = MIPS_CPU_ISA_IV;
mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
MIPS_CPU_FPU | MIPS_CPU_32FPR |
MIPS_CPU_COUNTER | MIPS_CPU_WATCH;
mips_cpu.tlbsize = 64;
break;
case PRID_IMP_R12000:
mips_cpu.cputype = CPU_R12000;
mips_cpu.isa_level = MIPS_CPU_ISA_IV;
mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
MIPS_CPU_FPU | MIPS_CPU_32FPR |
MIPS_CPU_COUNTER | MIPS_CPU_WATCH;
mips_cpu.tlbsize = 64;
break;
default:
mips_cpu.cputype = CPU_UNKNOWN;
break;
}
break;
#ifdef CONFIG_CPU_MIPS32
case PRID_COMP_MIPS:
switch (mips_cpu.processor_id & 0xff00) {
case PRID_IMP_4KC:
mips_cpu.cputype = CPU_4KC;
break;
case PRID_IMP_4KEC:
mips_cpu.cputype = CPU_4KEC;
break;
case PRID_IMP_4KSC:
mips_cpu.cputype = CPU_4KSC;
break;
case PRID_IMP_5KC:
mips_cpu.cputype = CPU_5KC;
mips_cpu.isa_level = MIPS_CPU_ISA_M64;
break;
case PRID_IMP_20KC:
mips_cpu.cputype = CPU_20KC;
mips_cpu.isa_level = MIPS_CPU_ISA_M64;
break;
default:
mips_cpu.cputype = CPU_UNKNOWN;
break;
}
break;
case PRID_COMP_ALCHEMY:
switch (mips_cpu.processor_id & 0xff00) {
case PRID_IMP_AU1_REV1:
case PRID_IMP_AU1_REV2:
if (mips_cpu.processor_id & 0xff000000)
mips_cpu.cputype = CPU_AU1500;
else
mips_cpu.cputype = CPU_AU1000;
break;
default:
mips_cpu.cputype = CPU_UNKNOWN;
break;
}
break;
#endif /* CONFIG_CPU_MIPS32 */
case PRID_COMP_SIBYTE:
switch (mips_cpu.processor_id & 0xff00) {
case PRID_IMP_SB1:
mips_cpu.cputype = CPU_SB1;
mips_cpu.isa_level = MIPS_CPU_ISA_M64;
mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
MIPS_CPU_COUNTER | MIPS_CPU_DIVEC |
MIPS_CPU_MCHECK;
#ifndef CONFIG_SB1_PASS_1_WORKAROUNDS
/* FPU in pass1 is known to have issues. */
mips_cpu.options |= MIPS_CPU_FPU;
#endif
break;
default:
mips_cpu.cputype = CPU_UNKNOWN;
break;
}
break;
default:
mips_cpu.cputype = CPU_UNKNOWN;
}
if (mips_cpu.options & MIPS_CPU_FPU)
mips_cpu.fpu_id = cpu_get_fpu_id();
}
