struct pdc_pat_pci_rt *
pdc_getirt(int *pn)
{
struct pdc_pat_pci_rt *rt;
int i, num, err;
long cell;
cell = -1;
if (!pdc_call((iodcio_t)pdc, 0, PDC_PAT_CELL, PDC_PAT_CELL_GETID,
&pdc_pat_cell_id, 0)) {
cell = pdc_pat_cell_id.id;
if ((err = pdc_call((iodcio_t)pdc, 0, PDC_PAT_IO,
PDC_PAT_IO_GET_PCI_RTSZ, &pdc_pat_io_num, cell))) {
printf("irt size error %d\n", err);
return (NULL);
}
} else if ((err = pdc_call((iodcio_t)pdc, 0, PDC_PCI_INDEX,
PDC_PCI_GET_INT_TBL_SZ, &pdc_pat_io_num, cpu_gethpa(0)))) {
printf("irt size error %d\n", err);
return (NULL);
}
printf("num %ld ", pdc_pat_io_num.num);
*pn = num = pdc_pat_io_num.num;
if (num > sizeof(pdc_rt) / sizeof(*rt)) {
printf("\nPCI IRT is too big %d\n", num);
return (NULL);
}
if (!(rt = malloc(num * sizeof(*rt), M_DEVBUF, M_NOWAIT)))
return (NULL);
if (cell >= 0) {
if ((err = pdc_call((iodcio_t)pdc, 0, PDC_PAT_IO,
PDC_PAT_IO_GET_PCI_RT, rt, cell))) {
printf("irt fetch error %d\n", err);
free(rt, M_DEVBUF);
return (NULL);
}
} else if ((err = pdc_call((iodcio_t)pdc, 0, PDC_PCI_INDEX,
PDC_PCI_GET_INT_TBL, &pdc_pat_io_num, cpu_gethpa(0), pdc_rt))) {
printf("irt fetch error %d\n", err);
free(rt, M_DEVBUF);
return (NULL);
}
bcopy(pdc_rt, rt, num * sizeof(*rt));
for (i = 0; i < num; i++)
printf("\n%d: ty 0x%02x it 0x%02x trig 0x%02x pin 0x%02x bus %d seg %d line %d addr 0x%llx",
i, rt[i].type, rt[i].itype, rt[i].trigger, rt[i].pin, rt[i].bus, rt[i].seg, rt[i].line, rt[i].addr);
return rt;
}
void
siop_sgc_attach(struct device *parent, struct device *self, void *aux)
{
struct siop_sgc_softc *sc = (struct siop_sgc_softc *)self;
struct confargs *ca = aux;
volatile struct iomod *regs;
sc->sc_iot = ca->ca_iot;
if (bus_space_map(sc->sc_iot, ca->ca_hpa,
IOMOD_HPASIZE, 0, &sc->sc_ioh)) {
printf(": cannot map io space\n");
return;
}
sc->sc_bustag = *sc->sc_iot;
sc->sc_bustag.hbt_r1 = siop_sgc_r1;
sc->sc_bustag.hbt_r2 = siop_sgc_r2;
sc->sc_bustag.hbt_w1 = siop_sgc_w1;
sc->sc_bustag.hbt_w2 = siop_sgc_w2;
sc->sc_siop.sc_c.features = SF_CHIP_PF | SF_CHIP_BE | SF_BUS_WIDE;
sc->sc_siop.sc_c.maxburst = 4;
sc->sc_siop.sc_c.maxoff = 8;
sc->sc_siop.sc_c.clock_div = 3;
sc->sc_siop.sc_c.clock_period = 250;
sc->sc_siop.sc_c.ram_size = 0;
sc->sc_siop.sc_c.sc_reset = siop_sgc_reset;
sc->sc_siop.sc_c.sc_dmat = ca->ca_dmatag;
sc->sc_siop.sc_c.sc_rt = &sc->sc_bustag;
bus_space_subregion(sc->sc_iot, sc->sc_ioh, IOMOD_DEVOFFSET,
IOMOD_HPASIZE - IOMOD_DEVOFFSET, &sc->sc_siop.sc_c.sc_rh);
regs = bus_space_vaddr(sc->sc_iot, sc->sc_ioh);
regs->io_command = CMD_RESET;
while ((regs->io_status & IO_ERR_MEM_RY) == 0)
delay(100);
regs->io_ii_rw = IO_II_PACKEN | IO_II_PREFETCHEN;
siop_sgc_reset(&sc->sc_siop.sc_c);
regs->io_eim = cpu_gethpa(0) | (31 - ca->ca_irq);
regs->io_ii_rw |= IO_II_INTEN;
cpu_intr_establish(IPL_BIO, ca->ca_irq, siop_intr, sc,
sc->sc_siop.sc_c.sc_dev.dv_xname);
printf(": NCR53C720 rev %d\n", bus_space_read_1(sc->sc_siop.sc_c.sc_rt,
sc->sc_siop.sc_c.sc_rh, SIOP_CTEST3) >> 4);
siop_attach(&sc->sc_siop);
}
int
apic_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp)
{
pci_chipset_tag_t pc = pa->pa_pc;
struct elroy_softc *sc = pc->_cookie;
pcitag_t tag = pa->pa_tag;
hppa_hpa_t hpa = cpu_gethpa(0);
pcireg_t reg;
reg = pci_conf_read(pc, tag, PCI_INTERRUPT_REG);
printf(" pin=%d line=%d ", PCI_INTERRUPT_PIN(reg), PCI_INTERRUPT_LINE(reg));
apic_write(sc->sc_regs, APIC_ENT0(PCI_INTERRUPT_PIN(reg)),
PCI_INTERRUPT_LINE(reg));
apic_write(sc->sc_regs, APIC_ENT1(PCI_INTERRUPT_PIN(reg)),
((hpa & 0x0ff00000) >> 4) | ((hpa & 0x000ff000) << 12));
*ihp = PCI_INTERRUPT_LINE(reg) + 1;
return (*ihp == 0);
}
void
waxattach(struct device *parent, struct device *self, void *aux)
{
struct confargs *ca = aux;
struct wax_softc *sc = (struct wax_softc *)self;
struct gsc_attach_args ga;
bus_space_handle_t ioh;
int s, in;
wax_attached = 1;
aprint_normal("\n");
/*
* Map the WAX interrupt registers.
*/
if (bus_space_map(ca->ca_iot, ca->ca_hpa, sizeof(struct wax_regs),
0, &ioh))
panic("waxattach: can't map interrupt registers");
sc->sc_regs = (struct wax_regs *)ca->ca_hpa;
/* interrupts guts */
s = splhigh();
sc->sc_regs->wax_iar = cpu_gethpa(0) | (31 - ca->ca_irq);
sc->sc_regs->wax_icr = 0;
sc->sc_regs->wax_imr = ~0U;
in = sc->sc_regs->wax_irr;
sc->sc_regs->wax_imr = 0;
splx(s);
/* Establish the interrupt register. */
hp700_intr_reg_establish(&sc->sc_int_reg);
sc->sc_int_reg.int_reg_mask = &sc->sc_regs->wax_imr;
sc->sc_int_reg.int_reg_req = &sc->sc_regs->wax_irr;
/* Attach the GSC bus. */
ga.ga_ca = *ca; /* clone from us */
ga.ga_name = "gsc";
ga.ga_int_reg = &sc->sc_int_reg;
ga.ga_fix_args = wax_fix_args;
ga.ga_fix_args_cookie = sc;
ga.ga_scsi_target = 7; /* XXX */
config_found(self, &ga, gscprint);
}
void *
apic_intr_establish(void *v, pci_intr_handle_t ih,
int pri, int (*handler)(void *), void *arg, const char *name)
{
struct elroy_softc *sc = v;
volatile struct elroy_regs *r = sc->sc_regs;
hppa_hpa_t hpa = cpu_gethpa(0);
struct evcount *cnt;
struct apic_iv *aiv, *biv;
void *iv;
int irq = APIC_INT_IRQ(ih);
int line = APIC_INT_LINE(ih);
u_int32_t ent0;
/* no mapping or bogus */
if (irq <= 0 || irq > 63)
return (NULL);
aiv = malloc(sizeof(struct apic_iv), M_DEVBUF, M_NOWAIT);
if (aiv == NULL) {
free(cnt, M_DEVBUF, 0);
return NULL;
}
aiv->sc = sc;
aiv->ih = ih;
aiv->handler = handler;
aiv->arg = arg;
aiv->next = NULL;
aiv->cnt = NULL;
if (apic_intr_list[irq]) {
cnt = malloc(sizeof(struct evcount), M_DEVBUF, M_NOWAIT);
if (!cnt) {
free(aiv, M_DEVBUF, 0);
return (NULL);
}
evcount_attach(cnt, name, NULL);
biv = apic_intr_list[irq];
while (biv->next)
biv = biv->next;
biv->next = aiv;
aiv->cnt = cnt;
return (arg);
}
if ((iv = cpu_intr_establish(pri, irq, apic_intr, aiv, name))) {
ent0 = (63 - irq) & APIC_ENT0_VEC;
ent0 |= apic_get_int_ent0(sc, line);
#if 0
if (cold) {
sc->sc_imr |= (1 << irq);
ent0 |= APIC_ENT0_MASK;
}
#endif
apic_write(sc->sc_regs, APIC_ENT0(line), APIC_ENT0_MASK);
apic_write(sc->sc_regs, APIC_ENT1(line),
((hpa & 0x0ff00000) >> 4) | ((hpa & 0x000ff000) << 12));
apic_write(sc->sc_regs, APIC_ENT0(line), ent0);
/* Signal EOI. */
elroy_write32(&r->apic_eoi,
htole32((63 - irq) & APIC_ENT0_VEC));
apic_intr_list[irq] = aiv;
}