static void __init at91sam9x5_register_clocks(void)
{
int i;
for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
clk_register(periph_clocks[i]);
clkdev_add_table(periph_clocks_lookups,
ARRAY_SIZE(periph_clocks_lookups));
clkdev_add_table(usart_clocks_lookups,
ARRAY_SIZE(usart_clocks_lookups));
if (cpu_is_at91sam9g25()
|| cpu_is_at91sam9x25())
clk_register(&usart3_clk);
if (cpu_is_at91sam9g25()
|| cpu_is_at91sam9x25()
|| cpu_is_at91sam9g35()
|| cpu_is_at91sam9x35())
clk_register(&macb0_clk);
if (cpu_is_at91sam9g15()
|| cpu_is_at91sam9g35()
|| cpu_is_at91sam9x35())
clk_register(&lcdc_clk);
if (cpu_is_at91sam9g25())
clk_register(&isi_clk);
if (cpu_is_at91sam9x25())
clk_register(&macb1_clk);
if (cpu_is_at91sam9x25()
|| cpu_is_at91sam9x35()) {
clk_register(&can0_clk);
clk_register(&can1_clk);
}
clk_register(&pck0);
clk_register(&pck1);
}
unsigned int has_lcdc()
{
return cpu_is_at91sam9g15() || cpu_is_at91sam9g35()
|| cpu_is_at91sam9x35();
}
unsigned int has_emac0()
{
return !(cpu_is_at91sam9g15());
}
void at91_add_device_eth(int id, struct macb_platform_data *data)
{
resource_size_t start;
if (!data)
return;
if (cpu_is_at91sam9g15())
return;
if (id && !cpu_is_at91sam9x25())
return;
switch (id) {
case 0:
start = AT91SAM9X5_BASE_EMAC0;
/* Pins used for MII and RMII */
at91_set_A_periph(AT91_PIN_PB4, 0); /* ETXCK_EREFCK */
at91_set_A_periph(AT91_PIN_PB3, 0); /* ERXDV */
at91_set_A_periph(AT91_PIN_PB0, 0); /* ERX0 */
at91_set_A_periph(AT91_PIN_PB1, 0); /* ERX1 */
at91_set_A_periph(AT91_PIN_PB2, 0); /* ERXER */
at91_set_A_periph(AT91_PIN_PB7, 0); /* ETXEN */
at91_set_A_periph(AT91_PIN_PB9, 0); /* ETX0 */
at91_set_A_periph(AT91_PIN_PB10, 0); /* ETX1 */
at91_set_A_periph(AT91_PIN_PB5, 0); /* EMDIO */
at91_set_A_periph(AT91_PIN_PB6, 0); /* EMDC */
if (data->phy_interface != PHY_INTERFACE_MODE_RMII) {
at91_set_A_periph(AT91_PIN_PB16, 0); /* ECRS */
at91_set_A_periph(AT91_PIN_PB17, 0); /* ECOL */
at91_set_A_periph(AT91_PIN_PB13, 0); /* ERX2 */
at91_set_A_periph(AT91_PIN_PB14, 0); /* ERX3 */
at91_set_A_periph(AT91_PIN_PB15, 0); /* ERXCK */
at91_set_A_periph(AT91_PIN_PB11, 0); /* ETX2 */
at91_set_A_periph(AT91_PIN_PB12, 0); /* ETX3 */
at91_set_A_periph(AT91_PIN_PB8, 0); /* ETXER */
}
break;
case 1:
start = AT91SAM9X5_BASE_EMAC1;
if (data->phy_interface != PHY_INTERFACE_MODE_RMII)
pr_warn("AT91: Only RMII available on interface macb%d.\n", id);
/* Pins used for RMII */
at91_set_B_periph(AT91_PIN_PC29, 0); /* ETXCK_EREFCK */
at91_set_B_periph(AT91_PIN_PC28, 0); /* ECRSDV */
at91_set_B_periph(AT91_PIN_PC20, 0); /* ERX0 */
at91_set_B_periph(AT91_PIN_PC21, 0); /* ERX1 */
at91_set_B_periph(AT91_PIN_PC16, 0); /* ERXER */
at91_set_B_periph(AT91_PIN_PC27, 0); /* ETXEN */
at91_set_B_periph(AT91_PIN_PC18, 0); /* ETX0 */
at91_set_B_periph(AT91_PIN_PC19, 0); /* ETX1 */
at91_set_B_periph(AT91_PIN_PC31, 0); /* EMDIO */
at91_set_B_periph(AT91_PIN_PC30, 0); /* EMDC */
break;
default:
return;
}
add_generic_device("macb", id, NULL, start, SZ_16K,
IORESOURCE_MEM, data);
}
