/* ------------------------------------------------------------------------*//** * @FUNCTION ctt44xx_dump * @BRIEF dump PRCM registers * @RETURNS 0 * OMAPCONF_ERR_CPU * OMAPCONF_ERR_REG_ACCESS * @DESCRIPTION dump PRCM registers *//*------------------------------------------------------------------------ */ int ctt44xx_dump(void) { unsigned int i = 0; unsigned int ret, val = 0; int err = 0; CHECK_CPU(44xx, OMAPCONF_ERR_ARG); printf("The Clock Tree Tool can import register settings from a *.rd1 " "file.\n"); printf("The format of the *.rd1 file is:\n\n"); printf("DeviceName OMAPxxxx_ESx.x\n"); printf("<register address> <register value>\n"); printf("<register address> <register value>\n"); printf("...\n\n"); printf("Copy the below output between the begin and end separators " "into a\n"); printf("file with the extension *.rd1 and this file can be read by the" "\n"); printf("Clock Tree Tool\n\n"); printf("|--------------------------- ctt dump begin ------------------" "----|\n"); if (cpu_is_omap4430()) printf("DeviceName OMAP4430_ES2.x\n"); else if (cpu_is_omap4460()) printf("DeviceName OMAP4460_ES1.x\n"); else if (cpu_is_omap4470()) printf("DeviceName OMAP4470_ES1.0\n"); else return OMAPCONF_ERR_CPU; ctt44xx_regtable_init(); while (prcm_ctt_reg_table[i].addr != 0) { /* display register addr & content (hex) */ ret = mem_read(prcm_ctt_reg_table[i].addr, &val); if (ret == 0) printf("0x%08X 0x%08X\n", prcm_ctt_reg_table[i].addr, val); else { fprintf(stderr, "omapconf: read error! (addr=0x%08X, err=%d)\n", prcm_ctt_reg_table[i].addr, ret); err = OMAPCONF_ERR_REG_ACCESS; } i++; } printf("|---------------------------- ctt dump end --------------------" "---|\n"); return err; }
/* ------------------------------------------------------------------------*//** * @FUNCTION ctt44xx_rd1_export * @BRIEF export PRCM registers in CTT RD1 format * @RETURNS 0 in case of success * OMAPCONF_ERR_CPU * OMAPCONF_ERR_REG_ACCESS * OMAPCONF_ERR_NOT_AVAILABLE * @param[in] filename: output file name * @DESCRIPTION export PRCM registers in CTT RD1 format *//*------------------------------------------------------------------------ */ int ctt44xx_rd1_export(char *filename) { unsigned int i = 0; unsigned int ret, val = 0; int err = 0; FILE *fd = NULL; CHECK_CPU(44xx, OMAPCONF_ERR_ARG); CHECK_NULL_ARG(filename, OMAPCONF_ERR_ARG); fd = fopen(filename, "w"); if (fd == NULL) { printf("error: could not create %s file!\n", filename); return OMAPCONF_ERR_NOT_AVAILABLE; } if (cpu_is_omap4430()) { fprintf(fd, "DeviceName OMAP4430_ES2.x\n"); } else if (cpu_is_omap4460()) { fprintf(fd, "DeviceName OMAP4460_ES1.x\n"); } else if (cpu_is_omap4470()) { fprintf(fd, "DeviceName OMAP4470_ES1.0\n"); } else { err = OMAPCONF_ERR_CPU; goto ctt44xx_rd1_export_end; } ctt44xx_regtable_init(); while (prcm_ctt_reg_table[i].addr != 0) { /* display register addr & content (hex) */ ret = mem_read(prcm_ctt_reg_table[i].addr, &val); if (ret == 0) fprintf(fd, "0x%08X 0x%08X\n", prcm_ctt_reg_table[i].addr, val); else { fprintf(stderr, "omapconf: read error! (addr=0x%08X, err=%d)\n", prcm_ctt_reg_table[i].addr, ret); err = OMAPCONF_ERR_REG_ACCESS; } i++; } printf("Output written to file '%s'.\n", filename); err = 0; ctt44xx_rd1_export_end: if (fd != NULL) fclose(fd); return err; }
/** * Function: dpll44xx_init_regtable * Role: initialize .addr field of reg_table (not possible statically) * Parameters: * none * Return: * 0 * OMAPCONF_ERR_CPU */ int dpll44xx_init_regtable(void) { unsigned int i = 0; CHECK_CPU(44xx, OMAPCONF_ERR_CPU); if (dpll44xx_prcm_reg_table_init_done == 1) return 0; /* Init DPLLs registers table */ dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_CLKMODE_DPLL_CORE; strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_CLKMODE_DPLL_CORE"); dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_IDLEST_DPLL_CORE; strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_IDLEST_DPLL_CORE"); dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_AUTOIDLE_DPLL_CORE; strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_AUTOIDLE_DPLL_CORE"); dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_CLKSEL_DPLL_CORE; strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_CLKSEL_DPLL_CORE"); dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_DIV_M2_DPLL_CORE; strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_DIV_M2_DPLL_CORE"); dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_DIV_M3_DPLL_CORE; strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_DIV_M3_DPLL_CORE"); dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_DIV_M4_DPLL_CORE; strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_DIV_M4_DPLL_CORE"); dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_DIV_M5_DPLL_CORE; strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_DIV_M5_DPLL_CORE"); dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_DIV_M6_DPLL_CORE; strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_DIV_M6_DPLL_CORE"); dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_DIV_M7_DPLL_CORE; strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_DIV_M7_DPLL_CORE"); dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE; strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_SSC_DELTAMSTEP_DPLL_CORE"); dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_SSC_MODFREQDIV_DPLL_CORE; strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_SSC_MODFREQDIV_DPLL_CORE"); dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_EMU_OVERRIDE_DPLL_CORE; strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_EMU_OVERRIDE_DPLL_CORE"); dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_CLKMODE_DPLL_PER; strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_CLKMODE_DPLL_PER"); dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_IDLEST_DPLL_PER; strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_IDLEST_DPLL_PER"); dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_AUTOIDLE_DPLL_PER; strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_AUTOIDLE_DPLL_PER"); dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_CLKSEL_DPLL_PER; strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_CLKSEL_DPLL_PER"); dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_DIV_M2_DPLL_PER; strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_DIV_M2_DPLL_PER"); dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_DIV_M3_DPLL_PER; strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_DIV_M3_DPLL_PER"); dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_DIV_M4_DPLL_PER; strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_DIV_M4_DPLL_PER"); dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_DIV_M5_DPLL_PER; strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_DIV_M5_DPLL_PER"); dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_DIV_M6_DPLL_PER; strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_DIV_M6_DPLL_PER"); dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_DIV_M7_DPLL_PER; strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_DIV_M7_DPLL_PER"); dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_SSC_DELTAMSTEP_DPLL_PER; strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_SSC_DELTAMSTEP_DPLL_PER"); dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_SSC_MODFREQDIV_DPLL_PER; strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_SSC_MODFREQDIV_DPLL_PER"); dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_EMU_OVERRIDE_DPLL_PER; strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_EMU_OVERRIDE_DPLL_PER"); dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_CLKMODE_DPLL_MPU; strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_CLKMODE_DPLL_MPU"); dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_IDLEST_DPLL_MPU; strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_IDLEST_DPLL_MPU"); dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_AUTOIDLE_DPLL_MPU; strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_AUTOIDLE_DPLL_MPU"); dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_CLKSEL_DPLL_MPU; strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_CLKSEL_DPLL_MPU"); dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_DIV_M2_DPLL_MPU; strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_DIV_M2_DPLL_MPU"); dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_SSC_DELTAMSTEP_DPLL_MPU; strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_SSC_DELTAMSTEP_DPLL_MPU"); dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_SSC_MODFREQDIV_DPLL_MPU; strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_SSC_MODFREQDIV_DPLL_MPU"); dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_BYPCLK_DPLL_MPU; strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_BYPCLK_DPLL_MPU"); dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_CLKMODE_DPLL_IVA; strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_CLKMODE_DPLL_IVA"); dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_IDLEST_DPLL_IVA; strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_IDLEST_DPLL_IVA"); dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_AUTOIDLE_DPLL_IVA; strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_AUTOIDLE_DPLL_IVA"); dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_CLKSEL_DPLL_IVA; strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_CLKSEL_DPLL_IVA"); dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_DIV_M4_DPLL_IVA; strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_DIV_M4_DPLL_IVA"); dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_DIV_M5_DPLL_IVA; strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_DIV_M5_DPLL_IVA"); dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_SSC_DELTAMSTEP_DPLL_IVA; strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_SSC_DELTAMSTEP_DPLL_IVA"); dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_SSC_MODFREQDIV_DPLL_IVA; strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_SSC_MODFREQDIV_DPLL_IVA"); dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_BYPCLK_DPLL_IVA; strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_BYPCLK_DPLL_IVA"); dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_CLKMODE_DPLL_ABE; strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_CLKMODE_DPLL_ABE"); dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_IDLEST_DPLL_ABE; strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_IDLEST_DPLL_ABE"); dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_AUTOIDLE_DPLL_ABE; strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_AUTOIDLE_DPLL_ABE"); dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_CLKSEL_DPLL_ABE; strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_CLKSEL_DPLL_ABE"); dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_DIV_M2_DPLL_ABE; strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_DIV_M2_DPLL_ABE"); dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_DIV_M3_DPLL_ABE; strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_DIV_M3_DPLL_ABE"); dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_SSC_DELTAMSTEP_DPLL_ABE; strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_SSC_DELTAMSTEP_DPLL_ABE"); dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_SSC_MODFREQDIV_DPLL_ABE; strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_SSC_MODFREQDIV_DPLL_ABE"); dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_CLKMODE_DPLL_USB; strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_CLKMODE_DPLL_USB"); dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_IDLEST_DPLL_USB; strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_IDLEST_DPLL_USB"); dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_AUTOIDLE_DPLL_USB; strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_AUTOIDLE_DPLL_USB"); dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_CLKSEL_DPLL_USB; strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_CLKSEL_DPLL_USB"); dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_DIV_M2_DPLL_USB; strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_DIV_M2_DPLL_USB"); dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_SSC_DELTAMSTEP_DPLL_USB; strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_SSC_DELTAMSTEP_DPLL_USB"); dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_SSC_MODFREQDIV_DPLL_USB; strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_SSC_MODFREQDIV_DPLL_USB"); if (cpu_is_omap4430() && (cpu_revision_get() == REV_ES1_0)) { dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_CLKMODE_DPLL_UNIPRO; strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_CLKMODE_DPLL_UNIPRO"); dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_IDLEST_DPLL_UNIPRO; strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_IDLEST_DPLL_UNIPRO"); dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_AUTOIDLE_DPLL_UNIPRO; strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_AUTOIDLE_DPLL_UNIPRO"); dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_CLKSEL_DPLL_UNIPRO; strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_CLKSEL_DPLL_UNIPRO"); dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_DIV_M2_DPLL_UNIPRO; strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_DIV_M2_DPLL_UNIPRO"); dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_SSC_DELTAMSTEP_DPLL_UNIPRO; strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_SSC_DELTAMSTEP_DPLL_UNIPRO"); dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_SSC_MODFREQDIV_DPLL_UNIPRO; strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_SSC_MODFREQDIV_DPLL_UNIPRO"); dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_CLKMODE_DPLL_DDRPHY; strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_CLKMODE_DPLL_DDRPHY"); dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_IDLEST_DPLL_DDRPHY; strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_IDLEST_DPLL_DDRPHY"); dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_AUTOIDLE_DPLL_DDRPHY; strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_AUTOIDLE_DPLL_DDRPHY"); dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_CLKSEL_DPLL_DDRPHY; strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_CLKSEL_DPLL_DDRPHY"); dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_DIV_M2_DPLL_DDRPHY; strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_DIV_M2_DPLL_DDRPHY"); dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_DIV_M4_DPLL_DDRPHY; strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_DIV_M4_DPLL_DDRPHY"); dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_DIV_M5_DPLL_DDRPHY; strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_DIV_M5_DPLL_DDRPHY"); dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_DIV_M6_DPLL_DDRPHY; strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_DIV_M6_DPLL_DDRPHY"); dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_SSC_DELTAMSTEP_DPLL_DDRPHY; strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_SSC_DELTAMSTEP_DPLL_DDRPHY"); dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_SSC_MODFREQDIV_DPLL_DDRPHY; strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_SSC_MODFREQDIV_DPLL_DDRPHY"); } dpll44xx_prcm_reg_table[i].addr = 0; strcpy(dpll44xx_prcm_reg_table[i].name, "END"); dpll44xx_prcm_reg_table_init_done = 1; return 0; }
/* ------------------------------------------------------------------------*//** * @FUNCTION core44xx_dependency_show * @BRIEF analyse CORE dependency configuration * @RETURNS 0 in case of success * OMAPCONF_ERR_CPU * OMAPCONF_ERR_REG_ACCESS * @param[in, out] stream: output file stream * @DESCRIPTION analyse CORE dependency configuration *//*------------------------------------------------------------------------ */ int core44xx_dependency_show(FILE *stream) { unsigned int cm_l3_1_dynamicdep; unsigned int cm_l3_2_dynamicdep; unsigned int cm_mpu_m3_staticdep; unsigned int cm_mpu_m3_dynamicdep; unsigned int cm_sdma_staticdep; unsigned int cm_sdma_dynamicdep; unsigned int cm_c2c_staticdep; unsigned int cm_c2c_dynamicdep; unsigned int cm_l4cfg_dynamicdep; int ret; CHECK_CPU(44xx, OMAPCONF_ERR_CPU); if (!init_done) core44xx_regtable_init(); ret = mem_read(OMAP4430_CM_L3_1_DYNAMICDEP, &cm_l3_1_dynamicdep); ret += mem_read(OMAP4430_CM_L3_2_DYNAMICDEP, &cm_l3_2_dynamicdep); ret += mem_read(OMAP4430_CM_MPU_M3_STATICDEP, &cm_mpu_m3_staticdep); ret += mem_read(OMAP4430_CM_MPU_M3_DYNAMICDEP, &cm_mpu_m3_dynamicdep); ret += mem_read(OMAP4430_CM_SDMA_STATICDEP, &cm_sdma_staticdep); ret += mem_read(OMAP4430_CM_SDMA_DYNAMICDEP, &cm_sdma_dynamicdep); ret += mem_read(OMAP4430_CM_C2C_STATICDEP, &cm_c2c_staticdep); ret += mem_read(OMAP4430_CM_C2C_DYNAMICDEP, &cm_c2c_dynamicdep); ret += mem_read(OMAP4430_CM_L4CFG_DYNAMICDEP, &cm_l4cfg_dynamicdep); if (ret != 0) return OMAPCONF_ERR_REG_ACCESS; fprintf(stream, "|-------------------------------------------------------------" "-------------|\n"); fprintf(stream, "| CORE Domain Dependency Configuration (Static/Dynamic) " " |\n"); fprintf(stream, "|-------------------------------------------------------------" "-------------|\n"); fprintf(stream, "| | FROM: " " |\n"); fprintf(stream, "| | L3_1 | L3_2 | MPU_M3 | SDMA | C2C" " | L4CFG |\n"); fprintf(stream, "| |Stat|Dyn |Stat|Dyn |Stat|Dyn |Stat|Dyn |Stat|" "Dyn |Stat|Dyn |\n"); fprintf(stream, "|-------------------------------------------------------------" "-------------|\n"); fprintf(stream, "| TOWARDS: | | | | | | | | | | " " | | |\n"); fprintf(stream, "| %-12s | %-3s|%-3s | %-3s|%-3s | %-3s|%-3s | %-3s|%-3s | %-3s" "|%-3s | %-3s|%-3s |\n", "MPU_M3", "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ ((extract_bit(cm_l3_2_dynamicdep, 0) == 1) ? "En" : "Dis"), "", /* not implemented */ "", /* not implemented */ ((extract_bit(cm_sdma_staticdep, 0) == 1) ? "En" : "Dis"), "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ "" /* not implemented */); fprintf(stream, "| %-12s | %-3s|%-3s | %-3s|%-3s | %-3s|%-3s | %-3s|%-3s | %-3s" "|%-3s | %-3s|%-3s |\n", "DSP", "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ ((extract_bit(cm_mpu_m3_staticdep, 1) == 1) ? "En" : "Dis"), "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ ((extract_bit(cm_l4cfg_dynamicdep, 1) == 1) ? "En" : "Dis")); fprintf(stream, "| %-12s | %-3s|%-3s | %-3s|%-3s | %-3s|%-3s | %-3s|%-3s | %-3s" "|%-3s | %-3s|%-3s |\n", "IVAHD", "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ ((extract_bit(cm_l3_2_dynamicdep, 2) == 1) ? "En" : "Dis"), ((extract_bit(cm_mpu_m3_staticdep, 2) == 1) ? "En" : "Dis"), "", /* not implemented */ ((extract_bit(cm_sdma_staticdep, 2) == 1) ? "En" : "Dis"), "", /* not implemented */ ((extract_bit(cm_c2c_staticdep, 2) == 1) ? "En" : "Dis"), "", /* not implemented */ "", /* not implemented */ "" /* not implemented */); fprintf(stream, "| %-12s | %-3s|%-3s | %-3s|%-3s | %-3s|%-3s | %-3s|%-3s | %-3s" "|%-3s | %-3s|%-3s |\n", "ABE", "", /* not implemented */ ((extract_bit(cm_l3_1_dynamicdep, 3) == 1) ? "En" : "Dis"), "", /* not implemented */ "", /* not implemented */ ((extract_bit(cm_mpu_m3_staticdep, 3) == 1) ? "En" : "Dis"), "", /* not implemented */ ((extract_bit(cm_sdma_staticdep, 3) == 1) ? "En" : "Dis"), "", /* not implemented */ ((extract_bit(cm_c2c_staticdep, 3) == 1) ? "En" : "Dis"), "", /* not implemented */ "", /* not implemented */ "" /* not implemented */); fprintf(stream, "| %-12s | %-3s|%-3s | %-3s|%-3s | %-3s|%-3s | %-3s|%-3s | %-3s" "|%-3s | %-3s|%-3s |\n", "MEM IF", "", /* not implemented */ ((extract_bit(cm_l3_1_dynamicdep, 4) == 1) ? "En" : "Dis"), "", /* not implemented */ "", /* not implemented */ ((extract_bit(cm_mpu_m3_staticdep, 4) == 1) ? "En" : "Dis"), "", /* not implemented */ ((extract_bit(cm_sdma_staticdep, 4) == 1) ? "En" : "Dis"), "", /* not implemented */ ((extract_bit(cm_c2c_staticdep, 4) == 1) ? "En" : "Dis"), ((extract_bit(cm_c2c_dynamicdep, 4) == 1) ? "En" : "Dis"), "", /* not implemented */ ((extract_bit(cm_l4cfg_dynamicdep, 4) == 1) ? "En" : "Dis")); fprintf(stream, "| %-12s | %-3s|%-3s | %-3s|%-3s | %-3s|%-3s | %-3s|%-3s | %-3s" "|%-3s | %-3s|%-3s |\n", "L3_1", "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ ((extract_bit(cm_l3_2_dynamicdep, 5) == 1) ? "En" : "Dis"), ((extract_bit(cm_mpu_m3_staticdep, 5) == 1) ? "En" : "Dis"), "", /* not implemented */ ((extract_bit(cm_sdma_staticdep, 5) == 1) ? "En" : "Dis"), "", /* not implemented */ ((extract_bit(cm_c2c_staticdep, 5) == 1) ? "En" : "Dis"), "", /* not implemented */ "", /* not implemented */ ((extract_bit(cm_l4cfg_dynamicdep, 5) == 1) ? "En" : "Dis")); fprintf(stream, "| %-12s | %-3s|%-3s | %-3s|%-3s | %-3s|%-3s | %-3s|%-3s | %-3s" "|%-3s | %-3s|%-3s |\n", "L3_2", "", /* not implemented */ ((extract_bit(cm_l3_1_dynamicdep, 6) == 1) ? "En" : "Dis"), "", /* not implemented */ "", /* not implemented */ ((extract_bit(cm_mpu_m3_staticdep, 6) == 1) ? "En" : "Dis"), ((extract_bit(cm_mpu_m3_dynamicdep, 6) == 1) ? "En" : "Dis"), ((extract_bit(cm_sdma_staticdep, 6) == 1) ? "En" : "Dis"), ((extract_bit(cm_sdma_dynamicdep, 6) == 1) ? "En" : "Dis"), ((extract_bit(cm_c2c_staticdep, 6) == 1) ? "En" : "Dis"), ((extract_bit(cm_c2c_dynamicdep, 6) == 1) ? "En" : "Dis"), "", /* not implemented */ ((extract_bit(cm_l4cfg_dynamicdep, 6) == 1) ? "En" : "Dis")); fprintf(stream, "| %-12s | %-3s|%-3s | %-3s|%-3s | %-3s|%-3s | %-3s|%-3s | %-3s" "|%-3s | %-3s|%-3s |\n", "L3INIT", "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ ((extract_bit(cm_l3_2_dynamicdep, 7) == 1) ? "En" : "Dis"), ((extract_bit(cm_mpu_m3_staticdep, 7) == 1) ? "En" : "Dis"), "", /* not implemented */ ((extract_bit(cm_sdma_staticdep, 7) == 1) ? "En" : "Dis"), "", /* not implemented */ ((extract_bit(cm_c2c_staticdep, 7) == 1) ? "En" : "Dis"), "", /* not implemented */ "", /* not implemented */ ((extract_bit(cm_l4cfg_dynamicdep, 7) == 1) ? "En" : "Dis")); fprintf(stream, "| %-12s | %-3s|%-3s | %-3s|%-3s | %-3s|%-3s | %-3s|%-3s | %-3s" "|%-3s | %-3s|%-3s |\n", "DSS", "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ ((extract_bit(cm_l3_2_dynamicdep, 8) == 1) ? "En" : "Dis"), ((extract_bit(cm_mpu_m3_staticdep, 8) == 1) ? "En" : "Dis"), "", /* not implemented */ ((extract_bit(cm_sdma_staticdep, 8) == 1) ? "En" : "Dis"), "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ ((extract_bit(cm_l4cfg_dynamicdep, 8) == 1) ? "En" : "Dis")); fprintf(stream, "| %-12s | %-3s|%-3s | %-3s|%-3s | %-3s|%-3s | %-3s|%-3s | %-3s" "|%-3s | %-3s|%-3s |\n", "ISS", "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ ((extract_bit(cm_l3_2_dynamicdep, 9) == 1) ? "En" : "Dis"), ((extract_bit(cm_mpu_m3_staticdep, 9) == 1) ? "En" : "Dis"), ((extract_bit(cm_mpu_m3_dynamicdep, 9) == 1) ? "En" : "Dis"), ((extract_bit(cm_sdma_staticdep, 9) == 1) ? "En" : "Dis"), "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ ((extract_bit(cm_l4cfg_dynamicdep, 9) == 1) ? "En" : "Dis")); fprintf(stream, "| %-12s | %-3s|%-3s | %-3s|%-3s | %-3s|%-3s | %-3s|%-3s | %-3s" "|%-3s | %-3s|%-3s |\n", "GFX", "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ ((extract_bit(cm_l3_2_dynamicdep, 10) == 1) ? "En" : "Dis"), ((extract_bit(cm_mpu_m3_staticdep, 10) == 1) ? "En" : "Dis"), "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ "" /* not implemented */); fprintf(stream, "| %-12s | %-3s|%-3s | %-3s|%-3s | %-3s|%-3s | %-3s|%-3s | %-3s" "|%-3s | %-3s|%-3s |\n", "SDMA", "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ ((extract_bit(cm_mpu_m3_staticdep, 11) == 1) ? "En" : "Dis"), "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ ((extract_bit(cm_l4cfg_dynamicdep, 11) == 1) ? "En" : "Dis")); fprintf(stream, "| %-12s | %-3s|%-3s | %-3s|%-3s | %-3s|%-3s | %-3s|%-3s | %-3s" "|%-3s | %-3s|%-3s |\n", "L4CFG", "", /* not implemented */ ((extract_bit(cm_l3_1_dynamicdep, 12) == 1) ? "En" : "Dis"), "", /* not implemented */ "", /* not implemented */ ((extract_bit(cm_mpu_m3_staticdep, 12) == 1) ? "En" : "Dis"), "", /* not implemented */ ((extract_bit(cm_sdma_staticdep, 12) == 1) ? "En" : "Dis"), "", /* not implemented */ ((extract_bit(cm_c2c_staticdep, 12) == 1) ? "En" : "Dis"), "", /* not implemented */ "", /* not implemented */ "" /* not implemented */); fprintf(stream, "| %-12s | %-3s|%-3s | %-3s|%-3s | %-3s|%-3s | %-3s|%-3s | %-3s" "|%-3s | %-3s|%-3s |\n", "L4PER", "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ ((extract_bit(cm_l3_2_dynamicdep, 13) == 1) ? "En" : "Dis"), ((extract_bit(cm_mpu_m3_staticdep, 13) == 1) ? "En" : "Dis"), "", /* not implemented */ ((extract_bit(cm_sdma_staticdep, 13) == 1) ? "En" : "Dis"), "", /* not implemented */ ((extract_bit(cm_c2c_staticdep, 13) == 1) ? "En" : "Dis"), "", /* not implemented */ "", /* not implemented */ "" /* not implemented */); fprintf(stream, "| %-12s | %-3s|%-3s | %-3s|%-3s | %-3s|%-3s | %-3s|%-3s | %-3s" "|%-3s | %-3s|%-3s |\n", "L4SEC", "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ ((extract_bit(cm_l3_2_dynamicdep, 14) == 1) ? "En" : "Dis"), ((extract_bit(cm_mpu_m3_staticdep, 14) == 1) ? "En" : "Dis"), "", /* not implemented */ ((extract_bit(cm_sdma_staticdep, 14) == 1) ? "En" : "Dis"), "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ "" /* not implemented */); fprintf(stream, "| %-12s | %-3s|%-3s | %-3s|%-3s | %-3s|%-3s | %-3s|%-3s | %-3s" "|%-3s | %-3s|%-3s |\n", "L4WKUP", "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ ((extract_bit(cm_mpu_m3_staticdep, 15) == 1) ? "En" : "Dis"), "", /* not implemented */ ((extract_bit(cm_sdma_staticdep, 15) == 1) ? "En" : "Dis"), "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ ((extract_bit(cm_l4cfg_dynamicdep, 15) == 1) ? "En" : "Dis")); fprintf(stream, "| %-12s | %-3s|%-3s | %-3s|%-3s | %-3s|%-3s | %-3s|%-3s | %-3s" "|%-3s | %-3s|%-3s |\n", "ALWONCORE", "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ ((extract_bit(cm_mpu_m3_staticdep, 16) == 1) ? "En" : "Dis"), "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ ((extract_bit(cm_l4cfg_dynamicdep, 16) == 1) ? "En" : "Dis")); fprintf(stream, "| %-12s | %-3s|%-3s | %-3s|%-3s | %-3s|%-3s | %-3s|%-3s | %-3s" "|%-3s | %-3s|%-3s |\n", "CEFUSE", "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ ((extract_bit(cm_mpu_m3_staticdep, 17) == 1) ? "En" : "Dis"), "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ ((extract_bit(cm_l4cfg_dynamicdep, 17) == 1) ? "En" : "Dis")); fprintf(stream, "| %-12s | %-3s|%-3s | %-3s|%-3s | %-3s|%-3s | %-3s|%-3s | %-3s" "|%-3s | %-3s|%-3s |\n", "C2C", "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ ((extract_bit(cm_l3_2_dynamicdep, 18) == 1) ? "En" : "Dis"), "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ ((extract_bit(cm_l4cfg_dynamicdep, 18) == 1) ? "En" : "Dis")); if (!cpu_is_omap4430()) fprintf(stream, "| %-12s | %-3s|%-3s | %-3s|%-3s | %-3s|%-3s | %-3s|" "%-3s | %-3s|%-3s | %-3s|%-3s |\n", "MPU", "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ "", /* not implemented */ ((extract_bit(cm_l4cfg_dynamicdep, 19) == 1) ? "En" : "Dis")); fprintf(stream, "|-------------------------------------------------------------" "-------------|\n"); fprintf(stream, "| Dynamic Dep | | | | | " " | |\n"); fprintf(stream, "| %-12s | %-2d | %-2d | %-2d | | " "%-2d | %-2d |\n", "Window Size", extract_bitfield(cm_l3_1_dynamicdep, 24, 4), extract_bitfield(cm_l3_2_dynamicdep, 24, 4), extract_bitfield(cm_mpu_m3_dynamicdep, 24, 4), extract_bitfield(cm_c2c_dynamicdep, 24, 4), extract_bitfield(cm_l4cfg_dynamicdep, 24, 4)); fprintf(stream, "|------------------------------------------------------------" "--------------|\n\n"); return 0; }
/* ------------------------------------------------------------------------*//** * @FUNCTION dpll_settings_extract * @BRIEF extract DPLL settings from registers * @RETURNS 0 in case of success * OMAPCONF_ERR_ARG * OMAPCONF_ERR_REG_ACCESS * @param[in] id: valid DPLL ID * @param[in] type: DPLL type * @param[in] dpll_regs: dpll registers to extract settings from * @param[in,out] settings: struct with extracted DPLL settings * @DESCRIPTION extract DPLL settings from registers *//*------------------------------------------------------------------------ */ int dpll_settings_extract(unsigned int id, dpll_type type, dpll_settings_regs *dpll_regs, dpll_settings *settings) { unsigned int val; CHECK_NULL_ARG(dpll_regs, OMAPCONF_ERR_ARG); CHECK_NULL_ARG(settings, OMAPCONF_ERR_ARG); settings->id = id; settings->type = type; /* Extract data from CM_CLKMODE_DPLL_xyz */ val = reg_read(dpll_regs->cm_clkmode_dpll); dprintf("%s(): DPLL reg: %s = 0x%08X\n", __func__, (dpll_regs->cm_clkmode_dpll)->name, val); settings->mode = extract_bitfield(val, 0, 3); (settings->ramp).ramp_level = extract_bitfield(val, 3, 2); (settings->ramp).ramp_rate = 1 << (extract_bitfield(val, 5, 3) + 1); settings->driftguard_en = extract_bit(val, 8); (settings->ramp).relock_ramp_en = extract_bit(val, 9); settings->lpmode_en = extract_bit(val, 10); settings->regm4xen = extract_bit(val, 11); (settings->SSC).mode = extract_bit(val, 12); (settings->SSC).ack = extract_bit(val, 13); (settings->SSC).downspread = extract_bit(val, 14); dprintf("%s(): mode=0x%X (%s), lp_mode=%u, REGM4XEN=%u, " "DRIFTGUARD_EN=%u\n", __func__, settings->mode, dpll_mode_name_get(settings->mode), settings->lpmode_en, settings->regm4xen, settings->driftguard_en); dprintf("%s(): RAMP_EN=%u, RAMP_RATE=%uxREFCLK, RAMP_LEVEL=%u (%s)\n", __func__, (settings->ramp).relock_ramp_en, (settings->ramp).ramp_rate, (settings->ramp).ramp_level, dpll_ramp_level_name_get((settings->ramp).ramp_level)); dprintf("%s(): SSC_EN=%u, SSC_ACK=%u, SSC_DOWNSPREAD=%u\n", __func__, (settings->SSC).mode, (settings->SSC).ack, (settings->SSC).downspread); /* Extract data from CM_IDLEST_DPLL_xyz */ val = reg_read(dpll_regs->cm_idlest_dpll); dprintf("%s(): DPLL reg: %s = 0x%08X\n", __func__, (dpll_regs->cm_idlest_dpll)->name, val); settings->lock_status = extract_bit(val, 0); settings->mn_bypass_status = extract_bit(val, 8); dprintf("%s(): ST_DPLL_CLK=%u, ST_MN_BYPASS=%u\n", __func__, settings->lock_status, settings->mn_bypass_status); /* Extract data from CM_AUTOIDLE_DPLL_xyz */ val = reg_read(dpll_regs->cm_autoidle_dpll); dprintf("%s(): DPLL reg: %s = 0x%08X\n", __func__, (dpll_regs->cm_autoidle_dpll)->name, val); settings->autoidle_mode = extract_bitfield(val, 0, 3); dprintf("%s(): AUTO_DPLL_MODE=%u (%s)\n", __func__, settings->autoidle_mode, dpll_autoidle_mode_name_get(settings->autoidle_mode)); /* Extract data from CM_CLKSEL_DPLL_xyz */ val = reg_read(dpll_regs->cm_clksel_dpll); dprintf("%s(): DPLL reg: %s = 0x%08X\n", __func__, (dpll_regs->cm_clksel_dpll)->name, val); if (settings->type == DPLL_TYPE_A) { (settings->MN).N = extract_bitfield(val, 0, 7); (settings->MN).M = extract_bitfield(val, 8, 11); settings->clkouthif_src = extract_bit(val, 20); if (!cpu_is_omap4430()) { (settings->DCC).en = extract_bit(val, 22); (settings->DCC).count = extract_bitfield(val, 24, 8); } else { (settings->DCC).en = 0; (settings->DCC).count = 0; } settings->bypass_clk = extract_bit(val, 23); } else { (settings->MN).N = extract_bitfield(val, 0, 8); (settings->MN).M = extract_bitfield(val, 8, 12); settings->selfreqdco = extract_bit(val, 21); settings->sd_div = extract_bitfield(val, 24, 8); dprintf("%s(): SELFREQDCO=%u, SD_DIV=%u\n", __func__, settings->selfreqdco, settings->sd_div); } dprintf("%s(): M=%u, N=%u, CLKOUTHIF_CLK=%u, BP_CLK=%u\n", __func__, (settings->MN).M, (settings->MN).N, settings->clkouthif_src, settings->bypass_clk); dprintf("%s(): DCC_EN=%u, DCC_COUNT=%u\n", __func__, (settings->DCC).en, (settings->DCC).count); /* Extract data from CM_BYPCLK_DPLL_XYZ */ if ((void *) dpll_regs->cm_bypclk_dpll != NULL) { val = reg_read(dpll_regs->cm_bypclk_dpll); dprintf("%s(): DPLL reg: %s = 0x%08X\n", __func__, (dpll_regs->cm_bypclk_dpll)->name, val); settings->bypass_clk_div = 1 << extract_bitfield(val, 0, 2); dprintf("%s(): BP_CLK_DIV=%u\n", __func__, settings->bypass_clk_div); } else { settings->bypass_clk_div = 1; dprintf("%s(): BYPCLK register does not exist.\n", __func__); } /* Extract data from CM_DIV_M2_DPLL_XYZ */ if ((void *) dpll_regs->cm_div_m2_dpll != NULL) { val = reg_read(dpll_regs->cm_div_m2_dpll); dprintf("%s(): DPLL reg: %s = 0x%08X\n", __func__, (dpll_regs->cm_div_m2_dpll)->name, val); (settings->MN).M2_present = 1; if (settings->type == DPLL_TYPE_A) { (settings->MN).M2 = extract_bitfield(val, 0, 5); (settings->MN).X2_M2_autogating = !extract_bit(val, 10); (settings->MN).X2_M2_clkout_st = extract_bit(val, 11); } else { (settings->MN).M2 = extract_bitfield(val, 0, 7); } (settings->MN).M2_autogating = !extract_bit(val, 8); (settings->MN).M2_clkout_st = extract_bit(val, 9); dprintf("%s(): M2 DIV=%u, AUTOGATING=%u, CLKST=%u\n", __func__, (settings->MN).M2, (settings->MN).M2_autogating, (settings->MN).M2_clkout_st); if (settings->type == DPLL_TYPE_A) { dprintf("%s(): X2_M2 AUTOGATING=%u, CLKST=%u\n", __func__, (settings->MN).X2_M2_autogating, (settings->MN).X2_M2_clkout_st); } } else { (settings->MN).M2_present = 0; dprintf("%s(): DIV_M2 register does not exist.\n", __func__); } /* Extract data from CM_DIV_M3_DPLL_XYZ */ if ((void *) dpll_regs->cm_div_m3_dpll != NULL) { val = reg_read(dpll_regs->cm_div_m3_dpll); dprintf("%s(): DPLL reg: %s = 0x%08X\n", __func__, (dpll_regs->cm_div_m3_dpll)->name, val); (settings->MN).M3_present = 1; (settings->MN).M3 = extract_bitfield(val, 0, 5); (settings->MN).X2_M3_autogating = !extract_bit(val, 8); (settings->MN).X2_M3_clkout_st = extract_bit(val, 9); dprintf("%s(): X2_M3 DIV=%u, AUTOGATING=%u, CLKST=%u\n", __func__, (settings->MN).M3, (settings->MN).X2_M3_autogating, (settings->MN).X2_M3_clkout_st); } else { (settings->MN).M3_present = 0; dprintf("%s(): DIV_M3 register does not exist.\n", __func__); } /* Extract data from CM_DELTAMSTEP_DPLL_xyz */ val = reg_read(dpll_regs->cm_ssc_deltamstep_dpll); dprintf("%s(): DPLL reg: %s = 0x%08X\n", __func__, (dpll_regs->cm_ssc_deltamstep_dpll)->name, val); (settings->SSC).deltaMStep = extract_bitfield(val, 0, 20); dprintf("%s(): deltaMStep=0x%X\n", __func__, (settings->SSC).deltaMStep); /* Extract data from CM_MODFREQDIV_DPLL_xyz */ val = reg_read(dpll_regs->cm_ssc_modfreqdiv_dpll); dprintf("%s(): DPLL reg: %s = 0x%08X\n", __func__, (dpll_regs->cm_ssc_modfreqdiv_dpll)->name, val); (settings->SSC).mantissa = extract_bitfield(val, 0, 7); (settings->SSC).exponent = extract_bitfield(val, 8, 3); dprintf("%s(): mantissa=0x%X, exponent=0x%X\n", __func__, (settings->SSC).mantissa, (settings->SSC).exponent); /* Extract data from CM_CLKDCOLDO_DPLL_xyz */ if ((void *) dpll_regs->cm_clkdcoldo_dpll != NULL) { val = reg_read(dpll_regs->cm_clkdcoldo_dpll); dprintf("%s(): DPLL reg: %s = 0x%08X\n", __func__, (dpll_regs->cm_clkdcoldo_dpll)->name, val); (settings->MN).clkdcoldo_autogating = !extract_bit(val, 8); (settings->MN).clkdcoldo_clkout_st = extract_bit(val, 9); dprintf("%s(): CLKDCOLDO AUTOGATING=%u, CLKST=%u\n", __func__, (settings->MN).clkdcoldo_autogating, (settings->MN).clkdcoldo_clkout_st); } return 0; }
/* ------------------------------------------------------------------------*//** * @FUNCTION mpu44xx_config_show * @BRIEF analyze MPU power configuration * @RETURNS 0 in case of success * OMAPCONF_ERR_CPU * OMAPCONF_ERR_REG_ACCESS * @param[in] stream: output file stream * @DESCRIPTION analyze MPU power configuration *//*------------------------------------------------------------------------ */ int mpu44xx_config_show(FILE *stream) { unsigned int pm_pda_cpu0_pwrstctrl; unsigned int pm_pda_cpu0_pwrstst; unsigned int rm_pda_cpu0_context; unsigned int cm_pda_cpu0_clkctrl; unsigned int cm_pda_cpu0_clkstctrl; unsigned int pm_pda_cpu1_pwrstctrl; unsigned int pm_pda_cpu1_pwrstst; unsigned int rm_pda_cpu1_context; unsigned int cm_pda_cpu1_clkctrl; unsigned int cm_pda_cpu1_clkstctrl; unsigned int scu_cpu_power_status; char s0[32], s1[32]; unsigned int cm_clkmode_dpll_mpu; unsigned int cm_idlest_dpll_mpu; unsigned int cm_autoidle_dpll_mpu; omap4_dpll_params dpll_mpu_params; unsigned int pm_pwstctrl; unsigned int pm_pwstst; unsigned int cm_clkstctrl; unsigned int rm_context; unsigned int cm_clkctrl; int ret; CHECK_CPU(44xx, OMAPCONF_ERR_CPU); if (!init_done) mpu44xx_regtable_init(); if (mem_read(OMAP4430_PM_PDA_CPU0_PWRSTCTRL, &pm_pda_cpu0_pwrstctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_PM_PDA_CPU0_PWRSTST, &pm_pda_cpu0_pwrstst) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_RM_PDA_CPU0_CPU0_CONTEXT, &rm_pda_cpu0_context) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_CM_PDA_CPU0_CPU0_CLKCTRL, &cm_pda_cpu0_clkctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_CM_PDA_CPU0_CLKSTCTRL, &cm_pda_cpu0_clkstctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_PM_PDA_CPU1_PWRSTCTRL, &pm_pda_cpu1_pwrstctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_PM_PDA_CPU1_PWRSTST, &pm_pda_cpu1_pwrstst) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_RM_PDA_CPU1_CPU1_CONTEXT, &rm_pda_cpu1_context) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_CM_PDA_CPU1_CPU1_CLKCTRL, &cm_pda_cpu1_clkctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_CM_PDA_CPU1_CLKSTCTRL, &cm_pda_cpu1_clkstctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_SCU_CPU_POWER_STATUS, &scu_cpu_power_status) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_CM_CLKMODE_DPLL_MPU, &cm_clkmode_dpll_mpu) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_CM_IDLEST_DPLL_MPU, &cm_idlest_dpll_mpu) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_CM_AUTOIDLE_DPLL_MPU, &cm_autoidle_dpll_mpu) != 0) return OMAPCONF_ERR_REG_ACCESS; ret = dpll44xx_dpll_params_get(DPLL44XX_MPU, &dpll_mpu_params, 0); if (ret < 0) return ret; /* MPU LPRM config */ fprintf(stream, "|----------------------------------------------------" "----|\n"); fprintf(stream, "| %-30s | %-9s | %-9s |\n", "MPU LPRM Configuration", "CPU0", "CPU1"); fprintf(stream, "|--------------------------------|-----------|-------" "----|\n"); pwrdm_state2string(s0, (pwrdm_state) extract_bitfield(pm_pda_cpu0_pwrstst, 0, 2)); pwrdm_state2string(s1, (pwrdm_state) extract_bitfield(pm_pda_cpu1_pwrstst, 0, 2)); fprintf(stream, "| %-30s | %-9s | %-9s |\n", "Current Power State", s0, s1); fprintf(stream, "| %-30s | %-9s | %-9s |\n", "Current Logic State", ((extract_bit(pm_pda_cpu0_pwrstst, 2) == 1) ? "ON" : "OFF"), ((extract_bit(pm_pda_cpu1_pwrstst, 2) == 1) ? "ON" : "OFF")); pwrdm_state2string(s0, (pwrdm_state) extract_bitfield(pm_pda_cpu0_pwrstst, 4, 2)); pwrdm_state2string(s1, (pwrdm_state) extract_bitfield(pm_pda_cpu1_pwrstst, 4, 2)); fprintf(stream, "| %-30s | %-9s | %-9s |\n", "Current L1$ State", s0, s1); pwrdm_state2string(s0, (pwrdm_state)extract_bitfield(pm_pda_cpu0_pwrstctrl, 0, 2)); pwrdm_state2string(s1, (pwrdm_state) extract_bitfield(pm_pda_cpu1_pwrstctrl, 0, 2)); fprintf(stream, "| %-30s | %-9s | %-9s |\n", "Standby Status", ((extract_bit(cm_pda_cpu0_clkctrl, 0) == 1) ? "STANDBY" : "RUNNING"), ((extract_bit(cm_pda_cpu1_clkctrl, 0) == 1) ? "STANDBY" : "RUNNING")); fprintf(stream, "| %-30s | %-9s | %-9s |\n", "", "", ""); fprintf(stream, "| %-30s | %-9s | %-9s |\n", "Target Power State", s0, s1); fprintf(stream, "| %-30s | %-9s | %-9s |\n", "Logic State When Domain is RET", ((extract_bit(pm_pda_cpu0_pwrstctrl, 2) == 1) ? "RET" : "OFF"), ((extract_bit(pm_pda_cpu1_pwrstctrl, 2) == 1) ? "RET" : "OFF")); fprintf(stream, "| %-30s | %-9s | %-9s |\n", "Clock Control", clkdm_ctrl_mode_name_get((clkdm_ctrl_mode) extract_bitfield(cm_pda_cpu0_clkstctrl, 0, 2)), clkdm_ctrl_mode_name_get((clkdm_ctrl_mode) extract_bitfield(cm_pda_cpu1_clkstctrl, 0, 2))); fprintf(stream, "| %-30s | %-9s | %-9s |\n", "", "", ""); if ((cpu_is_omap4430() && (cpu_revision_get() != REV_ES1_0)) || cpu_is_omap4460() || cpu_is_omap4470()) { pwrdm_state2string(s0, (pwrdm_state) extract_bitfield(pm_pda_cpu0_pwrstst, 24, 2)); pwrdm_state2string(s1, (pwrdm_state) extract_bitfield(pm_pda_cpu1_pwrstst, 24, 2)); fprintf(stream, "| %-30s | %-9s | %-9s |\n", "Last Power State", s0, s1); } fprintf(stream, "| %-30s | %-9s | %-9s |\n", "Last L1$ Context", ((extract_bit(rm_pda_cpu0_context, 8) == 1) ? "LOST" : "RETAINED"), ((extract_bit(rm_pda_cpu1_context, 8) == 1) ? "LOST" : "RETAINED")); fprintf(stream, "| %-30s | %-9s | %-9s |\n", "Last CPU Context", ((extract_bit(rm_pda_cpu0_context, 0) == 1) ? "LOST" : "RETAINED"), ((extract_bit(rm_pda_cpu1_context, 0) == 1) ? "LOST" : "RETAINED")); fprintf(stream, "|----------------------------------------------------" "----|\n"); fprintf(stream, "\n"); /* SCU Configuration */ fprintf(stream, "|----------------------------------------------------" "----|\n"); fprintf(stream, "| %-30s | %-9s | %-9s |\n", "SCU Configuration", "CPU0", "CPU1"); fprintf(stream, "|--------------------------------|-----------|-------" "----|\n"); OMAPCONF_SCU_CPU_POWER_STATUS_2_STRING(s0, extract_bitfield(scu_cpu_power_status, 0, 2)); OMAPCONF_SCU_CPU_POWER_STATUS_2_STRING(s1, extract_bitfield(scu_cpu_power_status, 8, 2)); fprintf(stream, "| %-30s | %-9s | %-9s |\n", "CPU Power Status", s0, s1); fprintf(stream, "|---------------------------------------------------" "-----|\n"); fprintf(stream, "\n"); /* MPU Power Domain Configuration */ if (mem_read(OMAP4430_PM_MPU_PWRSTCTRL, &pm_pwstctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_PM_MPU_PWRSTST, &pm_pwstst) != 0) return OMAPCONF_ERR_REG_ACCESS; ret = pwrdm44xx_config_show(stream, "MPU", OMAP4430_PM_MPU_PWRSTCTRL, pm_pwstctrl, OMAP4430_PM_MPU_PWRSTST, pm_pwstst); if (ret != 0) return ret; /* MPU Clock Domain Configuration */ if (mem_read(OMAP4430_CM_MPU_CLKSTCTRL, &cm_clkstctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; ret = clkdm44xx_config_show(stream, "MPU", OMAP4430_CM_MPU_CLKSTCTRL, cm_clkstctrl); if (ret != 0) return ret; /* MPU Module Power Configuration */ if (mem_read(OMAP4430_CM_MPU_MPU_CLKCTRL, &cm_clkctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_RM_MPU_MPU_CONTEXT, &rm_context) != 0) return OMAPCONF_ERR_REG_ACCESS; ret = mod44xx_config_show(stream, "MPU", OMAP4430_CM_MPU_MPU_CLKCTRL, cm_clkctrl, OMAP4430_RM_MPU_MPU_CONTEXT, rm_context); if (ret != 0) return ret; /* MPU DPLL Configuration */ fprintf(stream, "|----------------------------------------------------" "----|\n"); fprintf(stream, "| MPU DPLL Configuration " " |\n"); fprintf(stream, "|--------------------------------|-------------------" "----|\n"); fprintf(stream, "| %-30s | %-21s |\n", "Status", dpll_status_name_get((dpll_status) dpll_mpu_params.status)); sprintf(s0, "%d", (unsigned int) dpll_mpu_params.M2_speed); fprintf(stream, "| %-30s | %-21s |\n", "Clock Speed (MHz)", s0); fprintf(stream, "| %-30s | %-21s |\n", "Mode", dpll_mode_name_get((dpll_mode) dpll_mpu_params.mode)); fprintf(stream, "| %-30s | %-21s |\n", "Low-Power Mode", (dpll_mpu_params.lpmode == 1) ? "Enabled" : "Disabled"); fprintf(stream, "| %-30s | %-21s |\n", "Autoidle Mode", dpll_autoidle_mode_name_get((dpll_autoidle_mode) dpll_mpu_params.autoidle_mode)); fprintf(stream, "| %-30s | %-21s |\n", "M2 Output Autogating", (dpll_mpu_params.M2_autogating == 1) ? "Enabled" : "Disabled"); fprintf(stream, "|----------------------------------------------------" "----|\n"); fprintf(stream, "\nNB: type \"omapconf dplls cfg\" " "for detailed DPLL configuration.\n\n"); return 0; }
/* ------------------------------------------------------------------------*//** * @FUNCTION mpu44xx_regtable_init * @BRIEF initialize reg_table fields (not possible statically) * @RETURNS 0 in case of success * OMAPCONF_ERR_CPU * @DESCRIPTION initialize reg_table fields (not possible statically) *//*------------------------------------------------------------------------ */ int mpu44xx_regtable_init(void) { int i = 0; CHECK_CPU(44xx, OMAPCONF_ERR_CPU); /* Init PRCM MPU registers table */ strcpy(prcm_mpu_reg_table[i].name, "PM_PDA_CPU0_PWRSTCTRL"); prcm_mpu_reg_table[i++].addr = OMAP4430_PM_PDA_CPU0_PWRSTCTRL; strcpy(prcm_mpu_reg_table[i].name, "PM_PDA_CPU0_PWRSTST"); prcm_mpu_reg_table[i++].addr = OMAP4430_PM_PDA_CPU0_PWRSTST; strcpy(prcm_mpu_reg_table[i].name, "RM_PDA_CPU0_CONTEXT"); prcm_mpu_reg_table[i++].addr = OMAP4430_RM_PDA_CPU0_CPU0_CONTEXT; strcpy(prcm_mpu_reg_table[i].name, "RM_PDA_CPU0_RSTCTRL"); prcm_mpu_reg_table[i++].addr = OMAP4430_RM_PDA_CPU0_CPU0_RSTCTRL; strcpy(prcm_mpu_reg_table[i].name, "CM_PDA_CPU0_CLKCTRL"); prcm_mpu_reg_table[i++].addr = OMAP4430_CM_PDA_CPU0_CPU0_CLKCTRL; strcpy(prcm_mpu_reg_table[i].name, "CM_PDA_CPU0_CLKSTCTRL"); prcm_mpu_reg_table[i++].addr = OMAP4430_CM_PDA_CPU0_CLKSTCTRL; strcpy(prcm_mpu_reg_table[i].name, "PM_PDA_CPU1_PWRSTCTRL"); prcm_mpu_reg_table[i++].addr = OMAP4430_PM_PDA_CPU1_PWRSTCTRL; strcpy(prcm_mpu_reg_table[i].name, "PM_PDA_CPU1_PWRSTST"); prcm_mpu_reg_table[i++].addr = OMAP4430_PM_PDA_CPU1_PWRSTST; strcpy(prcm_mpu_reg_table[i].name, "RM_PDA_CPU1_CONTEXT"); prcm_mpu_reg_table[i++].addr = OMAP4430_RM_PDA_CPU1_CPU1_CONTEXT; strcpy(prcm_mpu_reg_table[i].name, "RM_PDA_CPU1_RSTCTRL"); prcm_mpu_reg_table[i++].addr = OMAP4430_RM_PDA_CPU1_CPU1_RSTCTRL; strcpy(prcm_mpu_reg_table[i].name, "CM_PDA_CPU1_CLKCTRL"); prcm_mpu_reg_table[i++].addr = OMAP4430_CM_PDA_CPU1_CPU1_CLKCTRL; strcpy(prcm_mpu_reg_table[i].name, "CM_PDA_CPU1_CLKSTCTRL"); prcm_mpu_reg_table[i++].addr = OMAP4430_CM_PDA_CPU1_CLKSTCTRL; strcpy(prcm_mpu_reg_table[i].name, "PM_MPU_PWRSTCTRL"); prcm_mpu_reg_table[i++].addr = OMAP4430_PM_MPU_PWRSTCTRL; strcpy(prcm_mpu_reg_table[i].name, "PM_MPU_PWRSTST"); prcm_mpu_reg_table[i++].addr = OMAP4430_PM_MPU_PWRSTST; strcpy(prcm_mpu_reg_table[i].name, "RM_MPU_MPU_CONTEXT"); prcm_mpu_reg_table[i++].addr = OMAP4430_RM_MPU_MPU_CONTEXT; strcpy(prcm_mpu_reg_table[i].name, "CM_MPU_CLKSTCTRL"); prcm_mpu_reg_table[i++].addr = OMAP4430_CM_MPU_CLKSTCTRL; strcpy(prcm_mpu_reg_table[i].name, "CM_MPU_MPU_CLKCTRL"); prcm_mpu_reg_table[i++].addr = OMAP4430_CM_MPU_MPU_CLKCTRL; strcpy(prcm_mpu_reg_table[i].name, "CM_MPU_STATICDEP"); prcm_mpu_reg_table[i++].addr = OMAP4430_CM_MPU_STATICDEP; strcpy(prcm_mpu_reg_table[i].name, "CM_MPU_DYNAMICDEP"); prcm_mpu_reg_table[i++].addr = OMAP4430_CM_MPU_DYNAMICDEP; strcpy(prcm_mpu_reg_table[i].name, "SCU_CPU_POWER_STATUS"); prcm_mpu_reg_table[i++].addr = OMAP4430_SCU_CPU_POWER_STATUS; strcpy(prcm_mpu_reg_table[i].name, "CM_CLKMODE_DPLL_MPU"); prcm_mpu_reg_table[i++].addr = OMAP4430_CM_CLKMODE_DPLL_MPU; strcpy(prcm_mpu_reg_table[i].name, "CM_IDLEST_DPLL_MPU"); prcm_mpu_reg_table[i++].addr = OMAP4430_CM_IDLEST_DPLL_MPU; strcpy(prcm_mpu_reg_table[i].name, "CM_AUTOIDLE_DPLL_MPU"); prcm_mpu_reg_table[i++].addr = OMAP4430_CM_AUTOIDLE_DPLL_MPU; strcpy(prcm_mpu_reg_table[i].name, "PRM_IRQSTATUS_MPU_A9"); prcm_mpu_reg_table[i++].addr = OMAP4430_PRM_IRQSTATUS_MPU; strcpy(prcm_mpu_reg_table[i].name, "PRM_IRQSTATUS_MPU_A9_2"); prcm_mpu_reg_table[i++].addr = OMAP4430_PRM_IRQSTATUS_MPU_2; strcpy(prcm_mpu_reg_table[i].name, "PRM_IRQENABLE_MPU_A9"); prcm_mpu_reg_table[i++].addr = OMAP4430_PRM_IRQENABLE_MPU; strcpy(prcm_mpu_reg_table[i].name, "PRM_IRQENABLE_MPU_A9_2"); prcm_mpu_reg_table[i++].addr = OMAP4430_PRM_IRQENABLE_MPU_2; strcpy(prcm_mpu_reg_table[i].name, "END"); prcm_mpu_reg_table[i].addr = 0; /* ES2.0 updates */ if ((cpu_is_omap4430() && (cpu_revision_get() != REV_ES1_0)) || cpu_is_omap4460() || cpu_is_omap4470()) { strcpy(omap44xx_prm_irq_names[22], "VC_CORE_VPACK"); strcpy(omap44xx_prm_irq_names[7], "RESERVED"); strcpy(omap44xx_prm_irq_names[5], "RESERVED"); } init_done = 1; return 0; }
/* One time initializations */ static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused) { struct omap_device *od; struct omap_system_dma_plat_info *p; struct resource *mem; char *name = "omap_dma_system"; dma_stride = OMAP2_DMA_STRIDE; dma_common_ch_start = CSDP; if (cpu_is_omap3630() || cpu_is_omap4430()) dma_common_ch_end = CCDN; else dma_common_ch_end = CCFN; p = kzalloc(sizeof(struct omap_system_dma_plat_info), GFP_KERNEL); if (!p) { pr_err("%s: Unable to allocate pdata for %s:%s\n", __func__, name, oh->name); return -ENOMEM; } p->dma_attr = (struct omap_dma_dev_attr *)oh->dev_attr; p->disable_irq_lch = omap2_disable_irq_lch; p->show_dma_caps = omap2_show_dma_caps; p->clear_dma = omap2_clear_dma; p->dma_write = dma_write; p->dma_read = dma_read; p->clear_lch_regs = NULL; p->errata = configure_dma_errata(); od = omap_device_build(name, 0, oh, p, sizeof(*p), omap2_dma_latency, ARRAY_SIZE(omap2_dma_latency), 0); kfree(p); if (IS_ERR(od)) { pr_err("%s: Can't build omap_device for %s:%s.\n", __func__, name, oh->name); return PTR_ERR(od); } mem = platform_get_resource(&od->pdev, IORESOURCE_MEM, 0); if (!mem) { dev_err(&od->pdev.dev, "%s: no mem resource\n", __func__); return -EINVAL; } dma_base = ioremap(mem->start, resource_size(mem)); if (!dma_base) { dev_err(&od->pdev.dev, "%s: ioremap fail\n", __func__); return -ENOMEM; } d = oh->dev_attr; d->chan = kzalloc(sizeof(struct omap_dma_lch) * (d->lch_count), GFP_KERNEL); if (!d->chan) { dev_err(&od->pdev.dev, "%s: kzalloc fail\n", __func__); return -ENOMEM; } return 0; }
/* ------------------------------------------------------------------------*//** * @FUNCTION pwrdm44xx_config_show * @BRIEF analyze power domain configuration * @RETURNS 0 in case of error * @param[in,out] stream: output file * @param[in,out] name: domain name * @param[in] pm_pwstctrl_addr: PM_xyz_PWSTCTRL register address * @param[in] pm_pwstctrl: PM_xyz_PWSTCTRL register content * @param[in] pm_pwstst_addr: PM_xyz_PWSTST register address * @param[in] pm_pwstst: PM_xyz_PWSTST register content * @DESCRIPTION analyze power domain configuration *//*------------------------------------------------------------------------ */ int pwrdm44xx_config_show(FILE *stream, const char name[11], unsigned int pm_pwstctrl_addr, unsigned int pm_pwstctrl, unsigned int pm_pwstst_addr, unsigned int pm_pwstst) { char curr[32], tgt[32], last[32]; dprintf("%s(): name=%s\n", __func__, name); dprintf("%s(): pm_pwstctrl addr=0x%08X\n", __func__, pm_pwstctrl_addr); dprintf("%s(): pm_pwstctrl=0x%08X\n", __func__, pm_pwstctrl); dprintf("%s(): pm_pwstst addr=0x%08X\n", __func__, pm_pwstst_addr); dprintf("%s(): pm_pwstst=0x%08X\n", __func__, pm_pwstst); dprintf("\n"); fprintf(stream, "|---------------------------------------------------" "-----------|\n"); fprintf(stream, "| %-10s Power Domain Configuration " " |\n", name); fprintf(stream, "|---------------------------------------------------" "-----------|\n"); fprintf(stream, "| %-30s | %-7s | %-7s | %-7s |\n", "Power State", "Current", "Target", "Last"); fprintf(stream, "|--------------------------------|---------|--------" "-|---------|\n"); pwrdm_state2string(curr, (pwrdm_state) extract_bitfield(pm_pwstst, 0, 2)); pwrdm_state2string(tgt, (pwrdm_state) extract_bitfield(pm_pwstctrl, 0, 2)); if ((cpu_is_omap4430() && (cpu_revision_get() != REV_ES1_0)) || cpu_is_omap4460() || cpu_is_omap4470()) { switch (pm_pwstst_addr) { case OMAP4430_PM_MPU_PWRSTST: case OMAP4430_PM_DSP_PWRSTST: case OMAP4430_PM_ABE_PWRSTST: case OMAP4430_PM_CORE_PWRSTST: case OMAP4430_PM_IVAHD_PWRSTST: case OMAP4430_PM_L3INIT_PWRSTST: case OMAP4430_PM_L4PER_PWRSTST: pwrdm_state2string(last, (pwrdm_state) extract_bitfield(pm_pwstst, 24, 2)); break; case OMAP4430_PM_CAM_PWRSTST: case OMAP4430_PM_DSS_PWRSTST: case OMAP4430_PM_GFX_PWRSTST: case OMAP4430_PM_EMU_PWRSTST: if (!cpu_is_omap4430()) pwrdm_state2string(last, (pwrdm_state) extract_bitfield(pm_pwstst, 24, 2)); else strcpy(last, ""); break; default: strcpy(last, ""); } } else { strcpy(last, ""); } fprintf(stream, "| %-30s | %-7s | %-7s | %-7s |\n", "Domain", curr, tgt, last); if ((pm_pwstctrl_addr == OMAP4430_PM_CAM_PWRSTCTRL) || (pm_pwstctrl_addr == OMAP4430_PM_EMU_PWRSTCTRL) || (pm_pwstctrl_addr == OMAP4430_PM_GFX_PWRSTCTRL)) { fprintf(stream, "| %-30s | %-7s | %-7s | |\n", "Logic", ((extract_bit(pm_pwstst, 2) == 1) ? "ON" : "OFF"), ""); } else { fprintf(stream, "| %-30s | %-7s | %-7s | |\n", "Logic", ((extract_bit(pm_pwstst, 2) == 1) ? "ON" : "OFF"), ((extract_bit(pm_pwstctrl, 2) == 1) ? "RET" : "OFF")); } fprintf(stream, "| %-30s | %-7s | %-7s | |\n", "Memory", "", ""); switch (pm_pwstctrl_addr) { case OMAP4430_PM_CORE_PWRSTCTRL: pwrdm_state2string(curr, (pwrdm_state) extract_bitfield(pm_pwstst, 12, 2)); pwrdm_state2string(tgt, (pwrdm_state) extract_bit(pm_pwstctrl, 12)); fprintf(stream, "| %-30s | %-7s | %-7s | |\n", " OCP_WP Bank & DMM Bank2", curr, tgt); break; default: break; } switch (pm_pwstctrl_addr) { case OMAP4430_PM_IVAHD_PWRSTCTRL: pwrdm_state2string(curr, (pwrdm_state) extract_bitfield(pm_pwstst, 10, 2)); pwrdm_state2string(tgt, (pwrdm_state) extract_bit(pm_pwstctrl, 11)); fprintf(stream, "| %-30s | %-7s | %-7s | |\n", " TCM2", curr, tgt); break; case OMAP4430_PM_CORE_PWRSTCTRL: pwrdm_state2string(curr, (pwrdm_state) extract_bitfield(pm_pwstst, 10, 2)); pwrdm_state2string(tgt, (pwrdm_state) extract_bit(pm_pwstctrl, 11)); fprintf(stream, "| %-30s | %-7s | %-7s | |\n", " MPU_M3 Unicache", curr, tgt); default: break; } switch (pm_pwstctrl_addr) { case OMAP4430_PM_MPU_PWRSTCTRL: pwrdm_state2string(curr, (pwrdm_state) extract_bitfield(pm_pwstst, 8, 2)); pwrdm_state2string(tgt, (pwrdm_state) extract_bit(pm_pwstctrl, 10)); fprintf(stream, "| %-30s | %-7s | %-7s | |\n", " RAM", curr, tgt); break; case OMAP4430_PM_DSP_PWRSTCTRL: pwrdm_state2string(curr, (pwrdm_state) extract_bitfield(pm_pwstst, 8, 2)); pwrdm_state2string(tgt, (pwrdm_state) extract_bit(pm_pwstctrl, 10)); fprintf(stream, "| %-30s | %-7s | %-7s | |\n", " EDMA", curr, tgt); break; case OMAP4430_PM_DSS_PWRSTCTRL: case OMAP4430_PM_CAM_PWRSTCTRL: case OMAP4430_PM_GFX_PWRSTCTRL: pwrdm_state2string(curr, (pwrdm_state) extract_bitfield(pm_pwstst, 4, 2)); pwrdm_state2string(tgt, (pwrdm_state) extract_bit(pm_pwstctrl, 8)); fprintf(stream, "| %-30s | %-7s | %-7s | |\n", " MEM", curr, tgt); break; case OMAP4430_PM_IVAHD_PWRSTCTRL: pwrdm_state2string(curr, (pwrdm_state) extract_bitfield(pm_pwstst, 8, 2)); pwrdm_state2string(tgt, (pwrdm_state) extract_bit(pm_pwstctrl, 10)); fprintf(stream, "| %-30s | %-7s | %-7s | |\n", " TCM1", curr, tgt); case OMAP4430_PM_CORE_PWRSTCTRL: pwrdm_state2string(curr, (pwrdm_state) extract_bitfield(pm_pwstst, 8, 2)); pwrdm_state2string(tgt, (pwrdm_state) extract_bit(pm_pwstctrl, 10)); fprintf(stream, "| %-30s | %-7s | %-7s | |\n", " MPU_M3 L2 RAM", curr, tgt); default: break; } switch (pm_pwstctrl_addr) { case OMAP4430_PM_ABE_PWRSTCTRL: pwrdm_state2string(curr, (pwrdm_state) extract_bitfield(pm_pwstst, 8, 2)); pwrdm_state2string(tgt, (pwrdm_state) extract_bit(pm_pwstctrl, 10)); fprintf(stream, "| %-30s | %-7s | %-7s | |\n", " PERIPHMEM", curr, tgt); pwrdm_state2string(curr, (pwrdm_state) extract_bitfield(pm_pwstst, 4, 2)); pwrdm_state2string(tgt, (pwrdm_state) extract_bit(pm_pwstctrl, 8)); fprintf(stream, "| %-30s | %-7s | %-7s | |\n", " AESSMEM", curr, tgt); break; case OMAP4430_PM_MPU_PWRSTCTRL: pwrdm_state2string(curr, (pwrdm_state) extract_bitfield(pm_pwstst, 6, 2)); pwrdm_state2string(tgt, (pwrdm_state) extract_bit(pm_pwstctrl, 9)); fprintf(stream, "| %-30s | %-7s | %-7s | |\n", " L2$", curr, tgt); if (cpu_is_omap4430()) pwrdm_state2string(curr, extract_bitfield(pm_pwstst, 4, 2)); else strcpy(curr, ""); /* not available on OMAP44[60-70] */ pwrdm_state2string(tgt, extract_bit(pm_pwstctrl, 8)); fprintf(stream, "| %-30s | %-7s | %-7s | |\n", " L1$", curr, tgt); break; case OMAP4430_PM_DSP_PWRSTCTRL: pwrdm_state2string(curr, (pwrdm_state) extract_bitfield(pm_pwstst, 6, 2)); pwrdm_state2string(tgt, (pwrdm_state) extract_bit(pm_pwstctrl, 9)); fprintf(stream, "| %-30s | %-7s | %-7s | |\n", " L2$", curr, tgt); pwrdm_state2string(curr, extract_bitfield(pm_pwstst, 4, 2)); pwrdm_state2string(tgt, extract_bit(pm_pwstctrl, 8)); fprintf(stream, "| %-30s | %-7s | %-7s | |\n", " L1$", curr, tgt); break; case OMAP4430_PM_IVAHD_PWRSTCTRL: pwrdm_state2string(curr, (pwrdm_state) extract_bitfield(pm_pwstst, 6, 2)); pwrdm_state2string(tgt, (pwrdm_state) extract_bit(pm_pwstctrl, 9)); fprintf(stream, "| %-30s | %-7s | %-7s | |\n", " SL2", curr, tgt); pwrdm_state2string(curr, (pwrdm_state) extract_bitfield(pm_pwstst, 4, 2)); pwrdm_state2string(tgt, (pwrdm_state) extract_bit(pm_pwstctrl, 8)); fprintf(stream, "| %-30s | %-7s | %-7s | |\n", " HWA", curr, tgt); break; case OMAP4430_PM_L4PER_PWRSTCTRL: pwrdm_state2string(curr, (pwrdm_state) extract_bitfield(pm_pwstst, 6, 2)); pwrdm_state2string(tgt, (pwrdm_state) extract_bit(pm_pwstctrl, 9)); fprintf(stream, "| %-30s | %-7s | %-7s | |\n", " NONRETAINED", curr, tgt); pwrdm_state2string(curr, (pwrdm_state) extract_bitfield(pm_pwstst, 4, 2)); pwrdm_state2string(tgt, (pwrdm_state) extract_bit(pm_pwstctrl, 8)); fprintf(stream, "| %-30s | %-7s | %-7s | |\n", " RETAINED", curr, tgt); break; case OMAP4430_PM_CORE_PWRSTCTRL: pwrdm_state2string(curr, (pwrdm_state) extract_bitfield(pm_pwstst, 6, 2)); pwrdm_state2string(tgt, (pwrdm_state) extract_bit(pm_pwstctrl, 9)); fprintf(stream, "| %-30s | %-7s | %-7s | |\n", " OCM RAM", curr, tgt); pwrdm_state2string(curr, (pwrdm_state) extract_bitfield(pm_pwstst, 4, 2)); pwrdm_state2string(tgt, (pwrdm_state) extract_bit(pm_pwstctrl, 8)); fprintf(stream, "| %-30s | %-7s | %-7s | |\n", " DMA/ICR Bank & DMM Bank1", curr, tgt); break; case OMAP4430_PM_L3INIT_PWRSTCTRL: pwrdm_state2string(curr, (pwrdm_state) extract_bitfield(pm_pwstst, 4, 2)); pwrdm_state2string(tgt, (pwrdm_state) extract_bit(pm_pwstctrl, 8)); fprintf(stream, "| %-30s | %-7s | %-7s | |\n", " L3INIT Bank1", curr, tgt); break; case OMAP4430_PM_EMU_PWRSTCTRL: pwrdm_state2string(curr, (pwrdm_state) extract_bitfield(pm_pwstst, 4, 2)); pwrdm_state2string(tgt, (pwrdm_state) extract_bitfield(pm_pwstctrl, 16, 2)); fprintf(stream, "| %-30s | %-7s | %-7s | |\n", " EMU Bank", curr, tgt); break; default: break; } fprintf(stream, "|---------------------------------------------------" "-----------|\n"); fprintf(stream, "| %-30s | %-27s |\n", "Ongoing Power Transition?", ((extract_bit(pm_pwstst, 20) == 1) ? "YES" : "NO")); fprintf(stream, "|---------------------------------------------------" "-----------|\n"); fprintf(stream, "\n"); return 0; }