void ti81xx_musb_phy_power(u8 on) { void __iomem *scm_base = NULL; u32 usbphycfg; scm_base = ioremap(TI81XX_SCM_BASE, SZ_2K); if (!scm_base) { pr_err("system control module ioremap failed\n"); return; } usbphycfg = __raw_readl(scm_base + USBCTRL0); if (on) { if (cpu_is_ti816x()) { usbphycfg |= TI816X_USBPHY0_NORMAL_MODE; usbphycfg &= ~TI816X_USBPHY_REFCLK_OSC; } else if (cpu_is_ti814x()) { usbphycfg &= ~(USBPHY_CM_PWRDN | USBPHY_OTG_PWRDN | USBPHY_DPINPUT | USBPHY_DMINPUT); usbphycfg |= (USBPHY_OTGVDET_EN | USBPHY_OTGSESSEND_EN | USBPHY_DPOPBUFCTL | USBPHY_DMOPBUFCTL); } } else { if (cpu_is_ti816x()) usbphycfg &= ~TI816X_USBPHY0_NORMAL_MODE; else if (cpu_is_ti814x()) usbphycfg |= USBPHY_CM_PWRDN | USBPHY_OTG_PWRDN; } __raw_writel(usbphycfg, scm_base + USBCTRL0); iounmap(scm_base); }
static int __init ti81xx_vpss_init(void) { /*FIXME add platform data here*/ int r; if (cpu_is_ti816x() || cpu_is_dm385()) { if (cpu_is_dm385()) vps_pdata.cpu = CPU_DM813X; else vps_pdata.cpu = CPU_DM816X; vps_pdata.numvencs = 4; vps_pdata.vencmask = (1 << VPS_DC_MAX_VENC) - 1; } else if (cpu_is_ti814x()) { vps_pdata.cpu = CPU_DM814X; vps_pdata.numvencs = 3; vps_pdata.vencmask = (1 << VPS_DC_MAX_VENC) - 1 \ - VPS_DC_VENC_HDCOMP; } vpss_device.dev.platform_data = &vps_pdata; r = platform_device_register(&vpss_device); if (r) printk(KERN_ERR "unable to register ti81xx_vpss device\n"); else printk(KERN_INFO "registered ti81xx_vpss device\n"); return r; }
/** * omap2_clksel_round_rate_div() - find divisor for the given clock and rate * @clk: OMAP struct clk to use * @target_rate: desired clock rate * @new_div: ptr to where we should store the divisor * * Finds 'best' divider value in an array based on the source and target * rates. The divider array must be sorted with smallest divider first. * This function is also used by the DPLL3 M2 divider code. * * Returns the rounded clock rate or returns 0xffffffff on error. */ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, u32 *new_div) { unsigned long test_rate; const struct clksel *clks; const struct clksel_rate *clkr; u32 last_div = 0; if (!clk->clksel || !clk->clksel_mask) return ~0; pr_debug("clock: clksel_round_rate_div: %s target_rate %ld\n", clk->name, target_rate); *new_div = 1; clks = _get_clksel_by_parent(clk, clk->parent); if (!clks) return ~0; for (clkr = clks->rates; clkr->div; clkr++) { if (!(clkr->flags & cpu_mask)) continue; /* Sanity check */ if (clkr->div <= last_div) pr_err("clock: clksel_rate table not sorted " "for clock %s", clk->name); last_div = clkr->div; test_rate = clk->parent->rate / clkr->div; if (test_rate <= target_rate) break; /* found it */ } if (!clkr->div) { if (!cpu_is_ti816x() && !cpu_is_ti814x()) pr_err("clock: Could not find divisor for target " "rate %ld for clock %s parent %s\n", target_rate, clk->name, clk->parent->name); return ~0; } *new_div = clkr->div; pr_debug("clock: new_div = %d, new_rate = %ld\n", *new_div, (clk->parent->rate / clkr->div)); return clk->parent->rate / clkr->div; }
static int __init ti81xx_vin_init(void) { int r; hdvpss_capture_dev.dev.platform_data = &ti81xx_hsvpss_capture_cfg; if (cpu_is_ti814x()) { hdvpss_capture_sdev_info[0].ti81xxvin_select_decoder = vps_ti814x_select_video_decoder; hdvpss_capture_sdev_info[0].ti81xxvin_set_mode = vps_ti814x_set_tvp7002_filter; hdvpss_capture_sdev_info[0].decoder_id = 0; hdvpss_capture_sdev_info[1].ti81xxvin_select_decoder = NULL; hdvpss_capture_sdev_info[1].ti81xxvin_set_mode = NULL; hdvpss_capture_sdev_info[1].decoder_id = 0; } else { #if 1 // SYNERGYS : Capture hdvpss_capture_sdev_info[0].ti81xxvin_select_decoder = NULL; hdvpss_capture_sdev_info[0].ti81xxvin_set_mode = NULL; #else hdvpss_capture_sdev_info[0].ti81xxvin_select_decoder = vps_ti816x_select_video_decoder; hdvpss_capture_sdev_info[0].ti81xxvin_set_mode = vps_ti816x_set_tvp7002_filter; #endif hdvpss_capture_sdev_info[0].decoder_id = 0; hdvpss_capture_sdev_info[1].ti81xxvin_select_decoder = NULL; hdvpss_capture_sdev_info[1].ti81xxvin_set_mode = NULL; hdvpss_capture_sdev_info[1].decoder_id = 0; } r = platform_device_register(&hdvpss_capture_dev); if (r) printk(KERN_ERR "unable to register ti81xx_vin device\n"); else printk(KERN_INFO "registered ti81xx_vin device\n"); return r; }
void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers) { struct omap2_hsmmc_info *c; int nr_hsmmc = ARRAY_SIZE(hsmmc_data); int i; u32 reg; if (!cpu_is_omap44xx()) { if (cpu_is_omap2430()) { control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE; control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1; } else { control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE; control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1; } } else { control_pbias_offset = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE; control_mmc1 = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1; reg = omap4_ctrl_pad_readl(control_mmc1); reg |= (OMAP4_SDMMC1_PUSTRENGTH_GRP0_MASK | OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK); reg &= ~(OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK | OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK); reg |= (OMAP4_USBC1_DR0_SPEEDCTRL_MASK| OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK | OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK); omap4_ctrl_pad_writel(reg, control_mmc1); } for (c = controllers; c->mmc; c++) { struct hsmmc_controller *hc = hsmmc + c->mmc - 1; struct omap_mmc_platform_data *mmc = hsmmc_data[c->mmc - 1]; if (!c->mmc || c->mmc > nr_hsmmc) { pr_debug("MMC%d: no such controller\n", c->mmc); continue; } if (mmc) { pr_debug("MMC%d: already configured\n", c->mmc); continue; } mmc = kzalloc(sizeof(struct omap_mmc_platform_data), GFP_KERNEL); if (!mmc) { pr_err("Cannot allocate memory for mmc device!\n"); goto done; } if (cpu_is_ti816x()) mmc->version = MMC_CTRL_VERSION_2; if (c->name) strncpy(hc->name, c->name, HSMMC_NAME_LEN); else snprintf(hc->name, ARRAY_SIZE(hc->name), "mmc%islot%i", c->mmc, 1); mmc->slots[0].name = hc->name; mmc->nr_slots = 1; mmc->slots[0].caps = c->caps; mmc->slots[0].internal_clock = !c->ext_clock; mmc->dma_mask = 0xffffffff; if (cpu_is_omap44xx()) mmc->reg_offset = OMAP4_MMC_REG_OFFSET; else mmc->reg_offset = 0; mmc->get_context_loss_count = hsmmc_get_context_loss; mmc->slots[0].switch_pin = c->gpio_cd; mmc->slots[0].gpio_wp = c->gpio_wp; mmc->slots[0].remux = c->remux; mmc->slots[0].init_card = c->init_card; if (c->cover_only) mmc->slots[0].cover = 1; if (c->nonremovable) mmc->slots[0].nonremovable = 1; if (c->power_saving) mmc->slots[0].power_saving = 1; if (c->no_off) mmc->slots[0].no_off = 1; if (c->vcc_aux_disable_is_sleep) mmc->slots[0].vcc_aux_disable_is_sleep = 1; /* NOTE: MMC slots should have a Vcc regulator set up. * This may be from a TWL4030-family chip, another * controllable regulator, or a fixed supply. * * temporary HACK: ocr_mask instead of fixed supply */ if (cpu_is_omap3505() || cpu_is_omap3517()) mmc->slots[0].ocr_mask = MMC_VDD_165_195 | MMC_VDD_26_27 | MMC_VDD_27_28 | MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32; else mmc->slots[0].ocr_mask = c->ocr_mask; if (cpu_is_omap3517() || cpu_is_omap3505() || cpu_is_ti81xx()) mmc->slots[0].set_power = nop_mmc_set_power; else mmc->slots[0].features |= HSMMC_HAS_PBIAS; if ((cpu_is_omap44xx() && (omap_rev() > OMAP4430_REV_ES1_0)) || cpu_is_ti814x()) mmc->slots[0].features |= HSMMC_HAS_UPDATED_RESET; switch (c->mmc) { case 1: if (mmc->slots[0].features & HSMMC_HAS_PBIAS) { /* on-chip level shifting via PBIAS0/PBIAS1 */ if (cpu_is_omap44xx()) { mmc->slots[0].before_set_reg = omap4_hsmmc1_before_set_reg; mmc->slots[0].after_set_reg = omap4_hsmmc1_after_set_reg; } else { mmc->slots[0].before_set_reg = omap_hsmmc1_before_set_reg; mmc->slots[0].after_set_reg = omap_hsmmc1_after_set_reg; } } /* Omap3630 HSMMC1 supports only 4-bit */ if (cpu_is_omap3630() && (c->caps & MMC_CAP_8_BIT_DATA)) { c->caps &= ~MMC_CAP_8_BIT_DATA; c->caps |= MMC_CAP_4_BIT_DATA; mmc->slots[0].caps = c->caps; } break; case 2: if (c->ext_clock) c->transceiver = 1; if (c->transceiver && (c->caps & MMC_CAP_8_BIT_DATA)) { c->caps &= ~MMC_CAP_8_BIT_DATA; c->caps |= MMC_CAP_4_BIT_DATA; } /* FALLTHROUGH */ case 3: if (mmc->slots[0].features & HSMMC_HAS_PBIAS) { /* off-chip level shifting, or none */ mmc->slots[0].before_set_reg = hsmmc23_before_set_reg; mmc->slots[0].after_set_reg = NULL; } break; default: pr_err("MMC%d configuration not supported!\n", c->mmc); kfree(mmc); continue; } hsmmc_data[c->mmc - 1] = mmc; } if (!cpu_is_ti81xx()) omap2_init_mmc(hsmmc_data, OMAP34XX_NR_MMC); else omap2_init_mmc(hsmmc_data, TI81XX_NR_MMC); /* pass the device nodes back to board setup code */ for (c = controllers; c->mmc; c++) { struct omap_mmc_platform_data *mmc = hsmmc_data[c->mmc - 1]; if (!c->mmc || c->mmc > nr_hsmmc) continue; c->dev = mmc->dev; } done: for (i = 0; i < nr_hsmmc; i++) kfree(hsmmc_data[i]); }
void __init omap2_init_common_infrastructure(void) { u8 postsetup_state; if (cpu_is_omap242x()) { omap2xxx_powerdomains_init(); omap2_clockdomains_init(); omap2420_hwmod_init(); } else if (cpu_is_omap243x()) { omap2xxx_powerdomains_init(); omap2_clockdomains_init(); omap2430_hwmod_init(); } else if (cpu_is_omap34xx()) { omap3xxx_powerdomains_init(); omap2_clockdomains_init(); omap3xxx_hwmod_init(); } else if (cpu_is_ti81xx()) { ti81xx_powerdomains_init(); omap2_clockdomains_init(); ti81xx_hwmod_init(); } else if (cpu_is_omap44xx()) { omap44xx_powerdomains_init(); omap44xx_clockdomains_init(); omap44xx_hwmod_init(); } else { pr_err("Could not init hwmod data - unknown SoC\n"); } /* Set the default postsetup state for all hwmods */ #ifdef CONFIG_PM_RUNTIME postsetup_state = _HWMOD_STATE_IDLE; #else postsetup_state = _HWMOD_STATE_ENABLED; #endif omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state); /* * Set the default postsetup state for unusual modules (like * MPU WDT). * * The postsetup_state is not actually used until * omap_hwmod_late_init(), so boards that desire full watchdog * coverage of kernel initialization can reprogram the * postsetup_state between the calls to * omap2_init_common_infra() and omap2_init_common_devices(). * * XXX ideally we could detect whether the MPU WDT was currently * enabled here and make this conditional */ postsetup_state = _HWMOD_STATE_DISABLED; omap_hwmod_for_each_by_class("wd_timer", _set_hwmod_postsetup_state, &postsetup_state); omap_pm_if_early_init(); if (cpu_is_omap2420()) omap2420_clk_init(); else if (cpu_is_omap2430()) omap2430_clk_init(); else if (cpu_is_omap34xx()) omap3xxx_clk_init(); else if (cpu_is_ti816x()) ti816x_clk_init(); else if (cpu_is_ti814x()) ti814x_clk_init(); else if (cpu_is_omap44xx()) omap4xxx_clk_init(); else pr_err("Could not init clock framework - unknown SoC\n"); }