static void cpu_mips_irq_request(void *opaque, int irq, int level) { CPUOldState *env = (CPUOldState *)opaque; if (irq < 0 || irq > 7) return; if (level) { env->CP0_Cause |= 1 << (irq + CP0Ca_IP); } else { env->CP0_Cause &= ~(1 << (irq + CP0Ca_IP)); } cpu_mips_update_irq(env); }
void cpu_mips_irq_request(void *opaque, int irq, int level) { CPUState *env = first_cpu; uint32_t mask; if (irq >= 16) return; mask = 1 << (irq + CP0Ca_IP); if (level) { env->CP0_Cause |= mask; } else { env->CP0_Cause &= ~mask; } cpu_mips_update_irq(env); }