static void m68k_cpu_realizefn(DeviceState *dev, Error **errp) { CPUState *cs = CPU(dev); M68kCPU *cpu = M68K_CPU(dev); M68kCPUClass *mcc = M68K_CPU_GET_CLASS(dev); Error *local_err = NULL; register_m68k_insns(&cpu->env); cpu_exec_realizefn(cs, &local_err); if (local_err != NULL) { error_propagate(errp, local_err); return; } m68k_cpu_init_gdb(cpu); cpu_reset(cs); qemu_init_vcpu(cs); mcc->parent_realize(dev, errp); }
static void ppce500_cpu_reset(void *opaque) { PowerPCCPU *cpu = opaque; CPUState *cs = CPU(cpu); CPUPPCState *env = &cpu->env; struct boot_info *bi = env->load_info; cpu_reset(cs); /* Set initial guest state. */ cs->halted = 0; env->gpr[1] = (16<<20) - 8; env->gpr[3] = bi->dt_base; env->gpr[4] = 0; env->gpr[5] = 0; env->gpr[6] = EPAPR_MAGIC; env->gpr[7] = mmubooke_initial_mapsize(env); env->gpr[8] = 0; env->gpr[9] = 0; env->nip = bi->entry; mmubooke_create_initial_mapping(env); }
int cpu_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { unsigned long cpuid; if (argc < 3) return cmd_usage(cmdtp); cpuid = simple_strtoul(argv[1], NULL, 10); if (cpuid >= cpu_numcores()) { printf ("Core num: %lu is out of range[0..%d]\n", cpuid, cpu_numcores() - 1); return 1; } if (argc == 3) { if (strncmp(argv[2], "reset", 5) == 0) cpu_reset(cpuid); else if (strncmp(argv[2], "status", 6) == 0) cpu_status(cpuid); else if (strncmp(argv[2], "disable", 7) == 0) return cpu_disable(cpuid); else return cmd_usage(cmdtp); return 0; } /* 4 or greater, make sure its release */ if (strncmp(argv[2], "release", 7) != 0) return cmd_usage(cmdtp); if (cpu_release(cpuid, argc - 3, argv + 3)) return cmd_usage(cmdtp); return 0; }
static void emu_main_loop_inner(void) { if (!emulationPaused) { if (cpuEvents & EVENT_RESET) { gui_console_printf("[CEmu] Calculator reset triggered...\n"); cpu_reset(); cpuEvents &= ~EVENT_RESET; } #ifdef DEBUG_SUPPORT if (!cpu.halted && (cpuEvents & EVENT_DEBUG_STEP)) { cpuEvents &= ~EVENT_DEBUG_STEP; open_debugger(DBG_STEP, 0); } #endif if (!asic.shipModeEnabled) { sched_process_pending_events(); cpu_execute(); } else { gui_emu_sleep(50); } } else { gui_emu_sleep(50); } }
static void s390_cpu_initfn(Object *obj) { S390CPU *cpu = S390_CPU(obj); CPUS390XState *env = &cpu->env; static int cpu_num = 0; #if !defined(CONFIG_USER_ONLY) struct tm tm; #endif cpu_exec_init(env); #if !defined(CONFIG_USER_ONLY) qemu_get_timedate(&tm, 0); env->tod_offset = TOD_UNIX_EPOCH + (time2tod(mktimegm(&tm)) * 1000000000ULL); env->tod_basetime = 0; env->tod_timer = qemu_new_timer_ns(vm_clock, s390x_tod_timer, cpu); env->cpu_timer = qemu_new_timer_ns(vm_clock, s390x_cpu_timer, cpu); #endif env->cpu_num = cpu_num++; env->ext_index = -1; cpu_reset(CPU(cpu)); }
static void tricore_cpu_realizefn(DeviceState *dev, Error **errp) { CPUState *cs = CPU(dev); TriCoreCPU *cpu = TRICORE_CPU(dev); TriCoreCPUClass *tcc = TRICORE_CPU_GET_CLASS(dev); CPUTriCoreState *env = &cpu->env; /* Some features automatically imply others */ if (tricore_feature(env, TRICORE_FEATURE_161)) { set_feature(env, TRICORE_FEATURE_16); } if (tricore_feature(env, TRICORE_FEATURE_16)) { set_feature(env, TRICORE_FEATURE_131); } if (tricore_feature(env, TRICORE_FEATURE_131)) { set_feature(env, TRICORE_FEATURE_13); } cpu_reset(cs); qemu_init_vcpu(cs); tcc->parent_realize(dev, errp); }
static void main_cpu_reset(void *opaque) { ResetData *s = (ResetData *)opaque; CPUSPARCState *env = &s->cpu->env; static unsigned int nr_resets; cpu_reset(CPU(s->cpu)); cpu_timer_reset(env->tick); cpu_timer_reset(env->stick); cpu_timer_reset(env->hstick); env->gregs[1] = 0; // Memory start env->gregs[2] = ram_size; // Memory size env->gregs[3] = 0; // Machine description XXX if (nr_resets++ == 0) { /* Power on reset */ env->pc = s->prom_addr + 0x20ULL; } else { env->pc = s->prom_addr + 0x40ULL; } env->npc = env->pc + 4; }
CPUM68KState *cpu_m68k_init(const char *cpu_model) { CPUM68KState *env; static int inited; env = qemu_mallocz(sizeof(CPUM68KState)); cpu_exec_init(env); if (!inited) { inited = 1; m68k_tcg_init(); } env->cpu_model_str = cpu_model; if (cpu_m68k_set_model(env, cpu_model) < 0) { cpu_m68k_close(env); return NULL; } cpu_reset(env); qemu_init_vcpu(env); return env; }
void machine_kexec(struct kimage *image) { unsigned long page_list; unsigned long reboot_code_buffer_phys; void *reboot_code_buffer; page_list = image->head & PAGE_MASK; /* we need both effective and real address here */ reboot_code_buffer_phys = page_to_pfn(image->control_code_page) << PAGE_SHIFT; reboot_code_buffer = page_address(image->control_code_page); /* Prepare parameters for reboot_code_buffer*/ kexec_start_address = image->start; kexec_indirection_page = page_list; kexec_mach_type = machine_arch_type; kexec_boot_atags = image->start - KEXEC_ARM_ZIMAGE_OFFSET + KEXEC_ARM_ATAGS_OFFSET; /* copy our kernel relocation code to the control code page */ memcpy(reboot_code_buffer, relocate_new_kernel, relocate_new_kernel_size); flush_icache_range((unsigned long) reboot_code_buffer, (unsigned long) reboot_code_buffer + KEXEC_CONTROL_PAGE_SIZE); printk(KERN_INFO "Bye!\n"); local_irq_disable(); local_fiq_disable(); setup_mm_for_reboot(0); /* mode is not used, so just pass 0*/ flush_cache_all(); cpu_proc_fin(); flush_cache_all(); cpu_reset(reboot_code_buffer_phys); }
Nios2CPU *cpu_nios2_init(const char *cpu_model) { Nios2CPU *cpu; int i; cpu = NIOS2_CPU(object_new(TYPE_NIOS2_CPU)); cpu->env.reset_addr = RESET_ADDRESS; cpu->env.exception_addr = EXCEPTION_ADDRESS; cpu->env.fast_tlb_miss_addr = FAST_TLB_MISS_ADDRESS; cpu_reset(CPU(cpu)); qemu_init_vcpu(CPU(cpu)); cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); for (i = 0; i < NUM_CORE_REGS; i++) { cpu_R[i] = tcg_global_mem_new(TCG_AREG0, offsetof(CPUNios2State, regs[i]), regnames[i]); } return cpu; }
/* * Reset the system. It is called by machine_restart(). */ void arch_reset(char mode, const char *cmd) { unsigned int wcr_enable; #ifdef CONFIG_MACH_MX51_EFIKAMX if (machine_is_mx51_efikamx()) { mx51_efikamx_reset(); return; } #endif if (cpu_is_mx1()) { wcr_enable = (1 << 0); } else { struct clk *clk; clk = clk_get_sys("imx2-wdt.0", NULL); if (!IS_ERR(clk)) clk_enable(clk); wcr_enable = (1 << 2); } /* Assert SRS signal */ __raw_writew(wcr_enable, wdog_base); /* wait for reset to assert... */ mdelay(500); printk(KERN_ERR "Watchdog reset failed to assert reset\n"); /* delay to allow the serial port to show the message */ mdelay(50); /* we'll take a jump through zero as a poor second */ cpu_reset(0); }
int main(void) { /* USER CODE BEGIN 1 */ my_usb_init(); /* USER CODE END 1 */ /* MCU Configuration----------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); /* Configure the system clock */ SystemClock_Config(); /* Initialize all configured peripherals */ MX_GPIO_Init(); MX_TIM1_Init(); MX_USB_DEVICE_Init(); MX_USART3_UART_Init(); MX_TIM2_Init(); /* USER CODE BEGIN 2 */ HAL_TIM_Base_Start(&htim2); delay_us_init(&htim2); softserial_init(SOFTSERIAL_TX_GPIO_Port, SOFTSERIAL_TX_Pin); hmi_lcd_init(&huart3); cpu_ctrl_init(&htim1); /* USER CODE END 2 */ /* Infinite loop */ /* USER CODE BEGIN WHILE */ HAL_Delay(100); hsc_stop(); cpu_reset(); lcd_clear(); addr_input(); data_input(); build_ui(); HAL_Delay(100); while (1) { /* USER CODE END WHILE */ /* USER CODE BEGIN 3 */ if(is_running == 0) addr_data_display_update(); // z80 reset button if(is_button_1_pressed) { hsc_stop(); cpu_reset(); lcd_print_width(130, 110, 180, 45, "CYAN", "RESET"); is_button_1_pressed = 0; HAL_Delay(500); build_ui(); } // clk step button if(is_button_3_pressed) { hsc_stop(); cycle_clock(1); lcd_print_width(130, 110, 180, 45, "RED", "CLK STEP"); is_button_3_pressed = 0; HAL_Delay(100); build_ui(); } // ins step button if(is_button_4_pressed) { hsc_stop(); lcd_print_width(130, 110, 180, 45, "GREEN", "INS STEP"); // cycle clock until we're at next M1 cycle while(HAL_GPIO_ReadPin(CPU_CTRL_PORT, M1_Pin) == LOW) cycle_clock(1); while(HAL_GPIO_ReadPin(CPU_CTRL_PORT, M1_Pin) == HIGH) cycle_clock(1); is_button_4_pressed = 0; HAL_Delay(100); build_ui(); } // run/stop button if(is_button_5_pressed) { is_running = (is_running + 1) % 2; if(is_running) { lcd_print_width(130, 110, 180, 45, "GREEN", "RUNNING"); hsc_start(); } else { hsc_stop(); build_ui(); } is_button_5_pressed = 0; } usb_data = my_usb_readline(); if(usb_data != NULL && strstr(usb_data, "epm") != NULL) { hsc_stop(); program_mode(); build_ui(); } } /* USER CODE END 3 */ }
void _exit(int status) { status = status; /* TODO save stack + assert info into nvram */ cpu_reset("SYSCALL EXIT"); }
static void s390_cpu_machine_reset_cb(void *opaque) { S390CPU *cpu = opaque; cpu_reset(CPU(cpu)); }
static void ppc_heathrow_reset(void *opaque) { PowerPCCPU *cpu = opaque; cpu_reset(CPU(cpu)); }
void cpu_reset2(const char *reason, int errcode) { //FIXME lame call, errcode discarded :/ cpu_reset(reason); }
static void main_cpu_reset(void *opaque) { CPUState *env = opaque; cpu_reset(env); env->sregs[SR_PC] = bootstrap_pc; }
void maincpu_reset(void) { cpu_reset(); }
/* * void cpu_reboot(int howto, char *bootstr) * * Reboots the system * * Deal with any syncing, unmounting, dumping and shutdown hooks, * then reset the CPU. */ void cpu_reboot(int howto, char *bootstr) { u_int32_t reg; #ifdef DIAGNOSTIC /* info */ printf("boot: howto=%08x curproc=%p\n", howto, curproc); #endif /* * If we are still cold then hit the air brakes * and crash to earth fast */ if (cold) { doshutdownhooks(); printf("The operating system has halted.\n"); printf("Please press any key to reboot.\n\n"); cngetc(); printf("rebooting...\n"); goto reset; } /* Disable console buffering */ /* * If RB_NOSYNC was not specified sync the discs. * Note: Unless cold is set to 1 here, syslogd will die during the * unmount. It looks like syslogd is getting woken up only to find * that it cannot page part of the binary in as the filesystem has * been unmounted. */ if (!(howto & RB_NOSYNC)) bootsync(); /* Say NO to interrupts */ splhigh(); /* Do a dump if requested. */ if ((howto & (RB_DUMP | RB_HALT)) == RB_DUMP) dumpsys(); /* Run any shutdown hooks */ doshutdownhooks(); /* Make sure IRQ's are disabled */ IRQdisable; if (howto & RB_HALT) { printf("The operating system has halted.\n"); printf("Please press any key to reboot.\n\n"); cngetc(); } printf("rebooting...\n\r"); reset: /* * Make really really sure that all interrupts are disabled, */ (void) disable_interrupts(I32_bit|F32_bit); IXPREG(IXP425_INT_ENABLE) = 0; /* * Map the boot Flash device down at physical address 0. * This is safe since NetBSD runs out of an alias of * SDRAM at 0x10000000. */ reg = EXP_CSR_READ_4(ixpsip_softc, EXP_CNFG0_OFFSET); reg |= EXP_CNFG0_MEM_MAP; EXP_CSR_WRITE_4(ixpsip_softc, EXP_CNFG0_OFFSET, reg); /* * Jump into the bootcode's reset vector * * XXX: * Redboot doesn't like the state in which we leave the PCI * ethernet card, and so fails to detect it on reboot. This * pretty much necessitates a hard reset/power cycle to be * able to download a new kernel image over ethernet. * * I suspect this is due to a bug in Redboot's i82557 driver. */ cpu_reset(); /* ...and if that didn't work, just croak. */ printf("RESET FAILED!\n"); for (;;); }
void http_settings(char *rx, unsigned int rx_len) { unsigned int item, found, len; int i; char buf[16]; MAC_Addr mac; IP_Addr ip; unsigned int rgb; for(; rx_len!=0;) { len = strlen("restartwebradio="); if(strncmpi(rx, "restartwebradio=", len) == 0) { rx += len; rx_len -= len; cpu_reset(); } for(item=0, found=0; item<SETTINGSITEMS; item++) { if(settingsmenu[item].ini[0] == 0) { continue; } len = sprintf(buf, "%s=", settingsmenu[item].ini); if(strncmpi(rx, buf, len) == 0) { rx += len; rx_len -= len; len = url_decode(rx, rx, rx_len); i = 0; switch(settingsmenu[item].format) { case F_NR: //p1-p2, p3=step size i = atoi(rx); if(i < settingsmenu[item].p1){ i = settingsmenu[item].p1; } else if(i > settingsmenu[item].p2){ i = settingsmenu[item].p2; } itoa(i, buf, 10); ini_setentry(SETTINGS_FILE, settingsmenu[item].ini, buf); if(settingsmenu[item].set){ settingsmenu[item].set((void*)(int)i); } break; case F_OR: //p1 or p2 i = atoi(rx); if((i != settingsmenu[item].p1) && (i != settingsmenu[item].p2)){ i = settingsmenu[item].p1; } itoa(i, buf, 10); ini_setentry(SETTINGS_FILE, settingsmenu[item].ini, buf); if(settingsmenu[item].set){ settingsmenu[item].set((void*)(int)i); } break; case F_STR: //p1=max len if((settingsmenu[item].p1 != 0) && (strlen(rx) > (unsigned)settingsmenu[item].p1)) { rx[settingsmenu[item].p1] = 0; } ini_setentry(SETTINGS_FILE, settingsmenu[item].ini, rx); if(settingsmenu[item].set){ settingsmenu[item].set(rx); } break; case F_MAC: mac = atomac(rx); ini_setentry(SETTINGS_FILE, settingsmenu[item].ini, mactoa(mac)); //if(settingsmenu[item].set){ settingsmenu[item].set((void*)(MAC_Addr)mac); } break; case F_IP: ip = atoip(rx); ini_setentry(SETTINGS_FILE, settingsmenu[item].ini, iptoa(ip)); if(settingsmenu[item].set){ settingsmenu[item].set((void*)(IP_Addr)atoip(rx)); } break; case F_RGB: rgb = atorgb(rx); sprintf(buf, "%03i,%03i,%03i", GET_RED(rgb), GET_GREEN(rgb), GET_BLUE(rgb)); ini_setentry(SETTINGS_FILE, settingsmenu[item].ini, buf); if(settingsmenu[item].set){ settingsmenu[item].set((void*)(unsigned int)rgb); } break; } rx += len; rx_len -= len; found = 1; break; } } if(found == 0) { rx++; rx_len--; } } menu_drawwnd(1); return; }
void ResetSystem(Serial *serial, unsigned int argc, char **argv) { cpu_reset(0); }
int arm_set_cpu_on(uint64_t cpuid, uint64_t entry, uint64_t context_id, uint32_t target_el, bool target_aa64) { CPUState *target_cpu_state; ARMCPU *target_cpu; DPRINTF("cpu %" PRId64 " (EL %d, %s) @ 0x%" PRIx64 " with R0 = 0x%" PRIx64 "\n", cpuid, target_el, target_aa64 ? "aarch64" : "aarch32", entry, context_id); /* requested EL level need to be in the 1 to 3 range */ assert((target_el > 0) && (target_el < 4)); if (target_aa64 && (entry & 3)) { /* * if we are booting in AArch64 mode then "entry" needs to be 4 bytes * aligned. */ return QEMU_ARM_POWERCTL_INVALID_PARAM; } /* Retrieve the cpu we are powering up */ target_cpu_state = arm_get_cpu_by_id(cpuid); if (!target_cpu_state) { /* The cpu was not found */ return QEMU_ARM_POWERCTL_INVALID_PARAM; } target_cpu = ARM_CPU(target_cpu_state); if (!target_cpu->powered_off) { qemu_log_mask(LOG_GUEST_ERROR, "[ARM]%s: CPU %" PRId64 " is already on\n", __func__, cpuid); return QEMU_ARM_POWERCTL_ALREADY_ON; } /* * The newly brought CPU is requested to enter the exception level * "target_el" and be in the requested mode (AArch64 or AArch32). */ if (((target_el == 3) && !arm_feature(&target_cpu->env, ARM_FEATURE_EL3)) || ((target_el == 2) && !arm_feature(&target_cpu->env, ARM_FEATURE_EL2))) { /* * The CPU does not support requested level */ return QEMU_ARM_POWERCTL_INVALID_PARAM; } if (!target_aa64 && arm_feature(&target_cpu->env, ARM_FEATURE_AARCH64)) { /* * For now we don't support booting an AArch64 CPU in AArch32 mode * TODO: We should add this support later */ qemu_log_mask(LOG_UNIMP, "[ARM]%s: Starting AArch64 CPU %" PRId64 " in AArch32 mode is not supported yet\n", __func__, cpuid); return QEMU_ARM_POWERCTL_INVALID_PARAM; } /* Initialize the cpu we are turning on */ cpu_reset(target_cpu_state); target_cpu->powered_off = false; target_cpu_state->halted = 0; if (target_aa64) { if ((target_el < 3) && arm_feature(&target_cpu->env, ARM_FEATURE_EL3)) { /* * As target mode is AArch64, we need to set lower * exception level (the requested level 2) to AArch64 */ target_cpu->env.cp15.scr_el3 |= SCR_RW; } if ((target_el < 2) && arm_feature(&target_cpu->env, ARM_FEATURE_EL2)) { /* * As target mode is AArch64, we need to set lower * exception level (the requested level 1) to AArch64 */ target_cpu->env.cp15.hcr_el2 |= HCR_RW; } target_cpu->env.pstate = aarch64_pstate_mode(target_el, true); } else { /* We are requested to boot in AArch32 mode */ static uint32_t mode_for_el[] = { 0, ARM_CPU_MODE_SVC, ARM_CPU_MODE_HYP, ARM_CPU_MODE_SVC }; cpsr_write(&target_cpu->env, mode_for_el[target_el], CPSR_M, CPSRWriteRaw); } if (target_el == 3) { /* Processor is in secure mode */ target_cpu->env.cp15.scr_el3 &= ~SCR_NS; } else { /* Processor is not in secure mode */ target_cpu->env.cp15.scr_el3 |= SCR_NS; } /* We check if the started CPU is now at the correct level */ assert(target_el == arm_current_el(&target_cpu->env)); if (target_aa64) { target_cpu->env.xregs[0] = context_id; target_cpu->env.thumb = false; } else { target_cpu->env.regs[0] = context_id; target_cpu->env.thumb = entry & 1; entry &= 0xfffffffe; } /* Start the new CPU at the requested address */ cpu_set_pc(target_cpu_state, entry); /* We are good to go */ return QEMU_ARM_POWERCTL_RET_SUCCESS; }
static void main_cpu_reset(void *opaque) { MoxieCPU *cpu = opaque; cpu_reset(CPU(cpu)); }
void cpu_reboot(int howto, char *bootstr) { #ifdef DIAGNOSTIC /* info */ printf("boot: howto=%08x curlwp=%p\n", howto, curlwp); #endif /* * If we are still cold then hit the air brakes * and crash to earth fast */ if (cold) { doshutdownhooks(); pmf_system_shutdown(boothowto); printf("The operating system has halted.\n"); printf("Please press any key to reboot.\n\n"); cngetc(); printf("rebooting...\n"); cpu_reset(); /*NOTREACHED*/ } /* Disable console buffering */ /* cnpollc(1);*/ /* * If RB_NOSYNC was not specified sync the discs. * Note: Unless cold is set to 1 here, syslogd will die during * the unmount. It looks like syslogd is getting woken up * only to find that it cannot page part of the binary in as * the filesystem has been unmounted. */ if (!(howto & RB_NOSYNC)) bootsync(); /* Say NO to interrupts */ splhigh(); /* Do a dump if requested. */ if ((howto & (RB_DUMP | RB_HALT)) == RB_DUMP) dumpsys(); /* Run any shutdown hooks */ doshutdownhooks(); pmf_system_shutdown(boothowto); /* Make sure IRQ's are disabled */ IRQdisable; if (howto & RB_HALT) { printf("The operating system has halted.\n"); printf("Please press any key to reboot.\n\n"); cngetc(); } printf("rebooting...\n"); cpu_reset(); /*NOTREACHED*/ }
static void ppc_core99_reset(void *opaque) { PowerPCCPU *cpu = opaque; cpu_reset(CPU(cpu)); }
void system_load_state(void *fd) { int i; uint8 reg[0x40]; /* Initialize everything */ cpu_reset(); system_reset(); /* Load VDP context */ fread(&vdp, sizeof(t_vdp), 1, fd); /* Load SMS context */ fread(&sms, sizeof(t_sms), 1, fd); /* Load Z80 context */ fread(Z80_Context, sizeof(Z80_Regs), 1, fd); fread(&after_EI, sizeof(int), 1, fd); /* Load YM2413 registers */ fread(reg, 0x40, 1, fd); /* Load SN76489 context */ fread(&sn[0], sizeof(t_SN76496), 1, fd); /* Restore callbacks */ z80_set_irq_callback(sms_irq_callback); cpu_readmap[0] = cart.rom + 0x0000; /* 0000-3FFF */ cpu_readmap[1] = cart.rom + 0x2000; cpu_readmap[2] = cart.rom + 0x4000; /* 4000-7FFF */ cpu_readmap[3] = cart.rom + 0x6000; cpu_readmap[4] = cart.rom + 0x0000; /* 0000-3FFF */ cpu_readmap[5] = cart.rom + 0x2000; cpu_readmap[6] = sms.ram; cpu_readmap[7] = sms.ram; cpu_writemap[0] = sms.dummy; cpu_writemap[1] = sms.dummy; cpu_writemap[2] = sms.dummy; cpu_writemap[3] = sms.dummy; cpu_writemap[4] = sms.dummy; cpu_writemap[5] = sms.dummy; cpu_writemap[6] = sms.ram; cpu_writemap[7] = sms.ram; sms_mapper_w(3, sms.fcr[3]); sms_mapper_w(2, sms.fcr[2]); sms_mapper_w(1, sms.fcr[1]); sms_mapper_w(0, sms.fcr[0]); /* Force full pattern cache update */ is_vram_dirty = 1; memset(vram_dirty, 1, 0x200); /* Restore palette */ for(i = 0; i < PALETTE_SIZE; i += 1) palette_sync(i); /* Restore sound state */ if(snd.enabled) { /* Clear YM2413 context */ OPLL_reset(opll) ; OPLL_reset_patch(opll,0) ; /* if use default voice data. */ /* Restore rhythm enable first */ ym2413_write(0, 0, 0x0E); ym2413_write(0, 1, reg[0x0E]); /* User instrument settings */ for(i = 0x00; i <= 0x07; i += 1) { ym2413_write(0, 0, i); ym2413_write(0, 1, reg[i]); } /* Channel frequency */ for(i = 0x10; i <= 0x18; i += 1) { ym2413_write(0, 0, i); ym2413_write(0, 1, reg[i]); } /* Channel frequency + ctrl. */ for(i = 0x20; i <= 0x28; i += 1) { ym2413_write(0, 0, i); ym2413_write(0, 1, reg[i]); } /* Instrument and volume settings */ for(i = 0x30; i <= 0x38; i += 1) { ym2413_write(0, 0, i); ym2413_write(0, 1, reg[i]); } } }
static void port92h_io_write(ioport_t port, Bit8u val) { int enA20 = (val & CONTROL_A20GATE_MASK) ? 1 : 0; if (val & CONTROL_RESET_MASK) cpu_reset(); set_a20(enA20); }
static void sim_reset(void *opaque) { XtensaCPU *cpu = opaque; cpu_reset(CPU(cpu)); }
static void db_reset(db_expr_t dummy1, boolean_t dummy2, db_expr_t dummy3, char * dummy4) { cpu_reset(); }
static void arm_cpu_realizefn(DeviceState *dev, Error **errp) { CPUState *cs = CPU(dev); ARMCPU *cpu = ARM_CPU(dev); ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev); CPUARMState *env = &cpu->env; /* Some features automatically imply others: */ if (arm_feature(env, ARM_FEATURE_V8)) { set_feature(env, ARM_FEATURE_V7); set_feature(env, ARM_FEATURE_ARM_DIV); set_feature(env, ARM_FEATURE_LPAE); set_feature(env, ARM_FEATURE_V8_AES); } if (arm_feature(env, ARM_FEATURE_V7)) { set_feature(env, ARM_FEATURE_VAPA); set_feature(env, ARM_FEATURE_THUMB2); set_feature(env, ARM_FEATURE_MPIDR); if (!arm_feature(env, ARM_FEATURE_M)) { set_feature(env, ARM_FEATURE_V6K); } else { set_feature(env, ARM_FEATURE_V6); } } if (arm_feature(env, ARM_FEATURE_V6K)) { set_feature(env, ARM_FEATURE_V6); set_feature(env, ARM_FEATURE_MVFR); } if (arm_feature(env, ARM_FEATURE_V6)) { set_feature(env, ARM_FEATURE_V5); if (!arm_feature(env, ARM_FEATURE_M)) { set_feature(env, ARM_FEATURE_AUXCR); } } if (arm_feature(env, ARM_FEATURE_V5)) { set_feature(env, ARM_FEATURE_V4T); } if (arm_feature(env, ARM_FEATURE_M)) { set_feature(env, ARM_FEATURE_THUMB_DIV); } if (arm_feature(env, ARM_FEATURE_ARM_DIV)) { set_feature(env, ARM_FEATURE_THUMB_DIV); } if (arm_feature(env, ARM_FEATURE_VFP4)) { set_feature(env, ARM_FEATURE_VFP3); } if (arm_feature(env, ARM_FEATURE_VFP3)) { set_feature(env, ARM_FEATURE_VFP); } if (arm_feature(env, ARM_FEATURE_LPAE)) { set_feature(env, ARM_FEATURE_V7MP); set_feature(env, ARM_FEATURE_PXN); } if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { set_feature(env, ARM_FEATURE_CBAR); } if (cpu->reset_hivecs) { cpu->reset_sctlr |= (1 << 13); } register_cp_regs_for_features(cpu); arm_cpu_register_gdb_regs_for_features(cpu); init_cpreg_list(cpu); cpu_reset(cs); qemu_init_vcpu(cs); acc->parent_realize(dev, errp); }