/* need test */
void pmrf_set_key(uint16_t addr, uint8_t *key)
{
uint8_t msg[16 + 2];
DEV_SPI_TRANSFER pmrf_xfer;
uint32_t cpu_status;
uint8_t i;
msg[0] = (uint8_t)(((addr >> 3) & 0x7F) | 0x80);
msg[1] = (uint8_t)(((addr << 5) & 0xE0) | (1 << 4));
for (i = 0; i < 16; i++)
{
msg[i + 2] = key[0];
}
DEV_SPI_XFER_SET_TXBUF(&pmrf_xfer, msg, 0, 18);
DEV_SPI_XFER_SET_RXBUF(&pmrf_xfer, NULL, 18, 0);
DEV_SPI_XFER_SET_NEXT(&pmrf_xfer, NULL);
#ifdef EMSK_PMRF_0_SPI_CPULOCK_ENABLE
cpu_status = cpu_lock_save();
#endif
pmrf_spi_ptr->spi_control(SPI_CMD_MST_SEL_DEV, CONV2VOID(cs_line));
pmrf_spi_ptr->spi_control(SPI_CMD_TRANSFER_POLLING, CONV2VOID(&pmrf_xfer));
pmrf_spi_ptr->spi_control(SPI_CMD_MST_DSEL_DEV, CONV2VOID(cs_line));
#ifdef EMSK_PMRF_0_SPI_CPULOCK_ENABLE
cpu_unlock_restore(cpu_status);
#endif
}
void pmrf_txfifo_write(uint16_t address, uint8_t *data, uint8_t hdr_len, uint8_t len)
{
uint8_t msg[len + 4];
DEV_SPI_TRANSFER pmrf_xfer;
uint32_t cpu_status;
uint8_t i = 0;
msg[0] = (uint8_t)(((address >> 3) & 0x7F) | 0x80);
msg[1] = (uint8_t)(((address << 5) & 0xE0) | (1 << 4));
msg[2] = hdr_len;
msg[3] = len;
for (i = 0; i < len; i++)
{
msg[i + 4] = *(data + i);
}
DEV_SPI_XFER_SET_TXBUF(&pmrf_xfer, msg, 0, len + 4);
DEV_SPI_XFER_SET_RXBUF(&pmrf_xfer, NULL, len + 4, 0);
DEV_SPI_XFER_SET_NEXT(&pmrf_xfer, NULL);
#ifdef EMSK_PMRF_0_SPI_CPULOCK_ENABLE
cpu_status = cpu_lock_save();
#endif
pmrf_spi_ptr->spi_control(SPI_CMD_MST_SEL_DEV, CONV2VOID(cs_line));
pmrf_spi_ptr->spi_control(SPI_CMD_TRANSFER_POLLING, CONV2VOID(&pmrf_xfer));
pmrf_spi_ptr->spi_control(SPI_CMD_MST_DSEL_DEV, CONV2VOID(cs_line));
#ifdef EMSK_PMRF_0_SPI_CPULOCK_ENABLE
cpu_unlock_restore(cpu_status);
#endif
}
/* need test */
void pmrf_txpkt_frame_write(uint8_t *frame, int16_t hdr_len, int16_t frame_len)
{
uint8_t msg[frame_len + 2 + 2];
DEV_SPI_TRANSFER pmrf_xfer;
uint32_t cpu_status;
uint8_t i = 0;
msg[0] = (uint8_t)(((MRF24J40_TXNFIFO >> 3) & 0x7F) | 0x80);
msg[1] = (uint8_t)(((MRF24J40_TXNFIFO << 5) & 0xE0) | (1 << 4));
msg[2] = (uint8_t)hdr_len;
msg[3] = (uint8_t)frame_len;
for (i = 0; i < frame_len; i++)
{
msg[i + 4] = *frame;
frame++;
}
DEV_SPI_XFER_SET_TXBUF(&pmrf_xfer, msg, 0, frame_len + 2 + 2);
DEV_SPI_XFER_SET_RXBUF(&pmrf_xfer, NULL, frame_len + 2 + 2, 0);
DEV_SPI_XFER_SET_NEXT(&pmrf_xfer, NULL);
#ifdef EMSK_PMRF_0_SPI_CPULOCK_ENABLE
cpu_status = cpu_lock_save();
#endif
pmrf_spi_ptr->spi_control(SPI_CMD_MST_SEL_DEV, CONV2VOID(cs_line));
pmrf_spi_ptr->spi_control(SPI_CMD_TRANSFER_POLLING, CONV2VOID(&pmrf_xfer));
pmrf_spi_ptr->spi_control(SPI_CMD_MST_DSEL_DEV, CONV2VOID(cs_line));
#ifdef EMSK_PMRF_0_SPI_CPULOCK_ENABLE
cpu_unlock_restore(cpu_status);
#endif
}
uint8_t pmrf_read_short_ctrl_reg(uint8_t addr)
{
uint8_t msg;
uint8_t ret_val;
DEV_SPI_TRANSFER pmrf_xfer;
uint32_t cpu_status;
msg = (((addr << 1) & 0x7E) | 0);
DEV_SPI_XFER_SET_TXBUF(&pmrf_xfer, &msg, 0, 1);
DEV_SPI_XFER_SET_RXBUF(&pmrf_xfer, &ret_val, 1, 1);
DEV_SPI_XFER_SET_NEXT(&pmrf_xfer, NULL);
#ifdef EMSK_PMRF_0_SPI_CPULOCK_ENABLE
cpu_status = cpu_lock_save();
#endif
pmrf_spi_ptr->spi_control(SPI_CMD_MST_SEL_DEV, CONV2VOID(cs_line));
pmrf_spi_ptr->spi_control(SPI_CMD_TRANSFER_POLLING, CONV2VOID(&pmrf_xfer));
pmrf_spi_ptr->spi_control(SPI_CMD_MST_DSEL_DEV, CONV2VOID(cs_line));
#ifdef EMSK_PMRF_0_SPI_CPULOCK_ENABLE
cpu_unlock_restore(cpu_status);
#endif
return ret_val;
}
void pmrf_write_short_ctrl_reg(uint8_t addr, uint8_t value)
{
DEV_SPI_TRANSFER pmrf_xfer;
uint8_t msg[3];
uint32_t cpu_status;
msg[0] = (((addr << 1) & 0x7E) | 1);
msg[1] = value;
msg[2] = 0x0; /* have to write 1 more byte, why ?*/
DEV_SPI_XFER_SET_TXBUF(&pmrf_xfer, msg, 0, 3);
DEV_SPI_XFER_SET_RXBUF(&pmrf_xfer, NULL, 3, 0);
DEV_SPI_XFER_SET_NEXT(&pmrf_xfer, NULL);
#ifdef EMSK_PMRF_0_SPI_CPULOCK_ENABLE
cpu_status = cpu_lock_save();
#endif
pmrf_spi_ptr->spi_control(SPI_CMD_MST_SEL_DEV, CONV2VOID(cs_line));
pmrf_spi_ptr->spi_control(SPI_CMD_TRANSFER_POLLING, CONV2VOID(&pmrf_xfer));
pmrf_spi_ptr->spi_control(SPI_CMD_MST_DSEL_DEV, CONV2VOID(cs_line));
#ifdef EMSK_PMRF_0_SPI_CPULOCK_ENABLE
cpu_unlock_restore(cpu_status);
#endif
}
uint8_t pmrf_read_long_ctrl_reg(uint16_t addr)
{
uint8_t msg[2];
uint8_t ret_val;
DEV_SPI_TRANSFER pmrf_xfer;
uint32_t cpu_status;
msg[0] = (uint8_t)(((addr >> 3) & 0x7F) | 0x80);
msg[1] = (uint8_t)((addr << 5) & 0xE0);
DEV_SPI_XFER_SET_TXBUF(&pmrf_xfer, msg, 0, 2);
DEV_SPI_XFER_SET_RXBUF(&pmrf_xfer, &ret_val, 2, 1);
DEV_SPI_XFER_SET_NEXT(&pmrf_xfer, NULL);
#ifdef EMSK_PMRF_0_SPI_CPULOCK_ENABLE
cpu_status = cpu_lock_save();
#endif
pmrf_spi_ptr->spi_control(SPI_CMD_MST_SEL_DEV, CONV2VOID(cs_line));
pmrf_spi_ptr->spi_control(SPI_CMD_TRANSFER_POLLING, CONV2VOID(&pmrf_xfer));
pmrf_spi_ptr->spi_control(SPI_CMD_MST_DSEL_DEV, CONV2VOID(cs_line));
#ifdef EMSK_PMRF_0_SPI_CPULOCK_ENABLE
cpu_unlock_restore(cpu_status);
#endif
return ret_val;
}
/* ----------------------------------------------------------------------------*/
void vPortYield(void)
{
unsigned int status32;
status32 = cpu_lock_save();
dispatch();
cpu_unlock_restore(status32);
}
/* ----------------------------------------------------------------------------*/
void vPortYieldFromIsr(void)
{
unsigned int status32;
status32 = cpu_lock_save();
context_switch_reqflg = true;
cpu_unlock_restore(status32);
}
static void timer_remove_from_master_list(KERNEL_TIMER_T * timer_p) {
KERNEL_TIMER_T * ptr;
CPU_LOCK_T lock;
cpu_lock_save(lock);
// If the timer is at the head of the list, remove it.
while (timer_list==timer_p) {
timer_list=timer_list->next;
}
// First timer in the list is not the one.
// Go through the list, looking for the one.
ptr=timer_list;
while (ptr!=NULL) {
if (ptr->next==timer_p) ptr->next=timer_p->next;
else ptr=ptr->next;
}
cpu_unlock_restore(lock);
}
static void timer_insert_into_master_list(KERNEL_TIMER_T * timer_p) {
CPU_LOCK_T lock;
KERNEL_TIMER_T ** p0;
KERNEL_TIMER_T * p1;
cpu_lock_save(lock);
// Start at the head, look at delivery times.
p0=&timer_list;
p1=timer_list;
while (1) {
if ((p1==NULL)||(clock_compare(&p1->delivery_time,&timer_p->delivery_time)>0)) {
// Insert our item between p0 and p1
timer_p->next=p1;
*p0=timer_p;
break; // out of the while (1) loop
}
p0=&(p1->next);
p1=p1->next;
}
cpu_unlock_restore(lock);
}
void pmrf_cs_pin(uint32_t flag)
{
uint32_t cpu_status;
#ifdef EMSK_PMRF_0_SPI_CPULOCK_ENABLE
cpu_status = cpu_lock_save();
#endif
if (flag == 1)
{
pmrf_spi_ptr->spi_control(SPI_CMD_MST_DSEL_DEV, CONV2VOID(cs_line));
}
else
{
pmrf_spi_ptr->spi_control(SPI_CMD_MST_SEL_DEV, CONV2VOID(cs_line));
}
#ifdef EMSK_PMRF_0_SPI_CPULOCK_ENABLE
cpu_unlock_restore(cpu_status);
#endif
}
/* need test */
void pmrf_rxpkt_intcb_frame_read(uint8_t *buf, uint8_t length)
{
uint8_t msg[length];
DEV_SPI_TRANSFER pmrf_xfer;
uint32_t cpu_status;
msg[0] = (uint8_t)((((MRF24J40_RXFIFO + 1) >> 3) & 0x7F) | 0x80);
msg[1] = (uint8_t)(((MRF24J40_RXFIFO + 1) << 5) & 0xE0);
DEV_SPI_XFER_SET_TXBUF(&pmrf_xfer, msg, 0, 2);
DEV_SPI_XFER_SET_RXBUF(&pmrf_xfer, buf, 2, length);
DEV_SPI_XFER_SET_NEXT(&pmrf_xfer, NULL);
#ifdef EMSK_PMRF_0_SPI_CPULOCK_ENABLE
cpu_status = cpu_lock_save();
#endif
pmrf_spi_ptr->spi_control(SPI_CMD_MST_SEL_DEV, CONV2VOID(cs_line));
pmrf_spi_ptr->spi_control(SPI_CMD_TRANSFER_POLLING, CONV2VOID(&pmrf_xfer));
pmrf_spi_ptr->spi_control(SPI_CMD_MST_DSEL_DEV, CONV2VOID(cs_line));
#ifdef EMSK_PMRF_0_SPI_CPULOCK_ENABLE
cpu_unlock_restore(cpu_status);
#endif
}
/** void sys_arch_unprotect(sys_prot_t pval)
This optional function does a "fast" set of critical region protection to the
value specified by pval. See the documentation for sys_arch_protect() for
more information. This function is only required if your port is supporting
an operating system.
*/
void sys_arch_unprotect(sys_prot_t pval)
{
cpu_unlock_restore(pval);
}