static void __init ms_hyperv_init_platform(void) { int hv_host_info_eax; int hv_host_info_ebx; int hv_host_info_ecx; int hv_host_info_edx; /* * Extract the features and hints */ ms_hyperv.features = cpuid_eax(HYPERV_CPUID_FEATURES); ms_hyperv.misc_features = cpuid_edx(HYPERV_CPUID_FEATURES); ms_hyperv.hints = cpuid_eax(HYPERV_CPUID_ENLIGHTMENT_INFO); pr_info("HyperV: features 0x%x, hints 0x%x\n", ms_hyperv.features, ms_hyperv.hints); /* * Extract host information. */ if (cpuid_eax(HVCPUID_VENDOR_MAXFUNCTION) >= HVCPUID_VERSION) { hv_host_info_eax = cpuid_eax(HVCPUID_VERSION); hv_host_info_ebx = cpuid_ebx(HVCPUID_VERSION); hv_host_info_ecx = cpuid_ecx(HVCPUID_VERSION); hv_host_info_edx = cpuid_edx(HVCPUID_VERSION); pr_info("Hyper-V Host Build:%d-%d.%d-%d-%d.%d\n", hv_host_info_eax, hv_host_info_ebx >> 16, hv_host_info_ebx & 0xFFFF, hv_host_info_ecx, hv_host_info_edx >> 24, hv_host_info_edx & 0xFFFFFF); }
static int __init amd_power_pmu_init(void) { int ret; if (!x86_match_cpu(cpu_match)) return 0; if (!boot_cpu_has(X86_FEATURE_ACC_POWER)) return -ENODEV; cpu_pwr_sample_ratio = cpuid_ecx(0x80000007); if (rdmsrl_safe(MSR_F15H_CU_MAX_PWR_ACCUMULATOR, &max_cu_acc_power)) { pr_err("Failed to read max compute unit power accumulator MSR\n"); return -ENODEV; } cpuhp_setup_state(CPUHP_AP_PERF_X86_AMD_POWER_ONLINE, "perf/x86/amd/power:online", power_cpu_init, power_cpu_exit); ret = perf_pmu_register(&pmu_class, "power", -1); if (WARN_ON(ret)) { pr_warn("AMD Power PMU registration failed\n"); return ret; } pr_info("AMD Power PMU detected\n"); return ret; }
void intel_model_2065x_finalize_smm(void) { msr_set_bit(MSR_PMG_CST_CONFIG_CONTROL, 15); /* Lock AES-NI only if supported */ if (cpuid_ecx(1) & (1 << 25)) msr_set_bit(MSR_FEATURE_CONFIG, 0); #ifdef LOCK_POWER_CONTROL_REGISTERS /* * Lock the power control registers. * * These registers can be left unlocked if modifying power * limits from the OS is desirable. Modifying power limits * from the OS can be especially useful for experimentation * during early phases of system bringup while the thermal * power envelope is being proven. */ msr_set_bit(MSR_PP0_CURRENT_CONFIG, 31); msr_set_bit(MSR_PP1_CURRENT_CONFIG, 31); msr_set_bit(MSR_PKG_POWER_LIMIT, 63); msr_set_bit(MSR_PP0_POWER_LIMIT, 31); msr_set_bit(MSR_PP1_POWER_LIMIT, 31); #endif msr_set_bit(MSR_MISC_PWR_MGMT, 22); msr_set_bit(MSR_LT_LOCK_MEMORY, 0); }
static void model_10_init(device_t dev) { printk(BIOS_DEBUG, "Model 10 Init - a no-op.\n"); u8 i; msr_t msr; #if CONFIG_LOGICAL_CPUS u32 siblings; #endif /* Turn on caching if we haven't already */ x86_enable_cache(); amd_setup_mtrrs(); x86_mtrr_check(); disable_cache(); /* zero the machine check error status registers */ msr.lo = 0; msr.hi = 0; for (i = 0; i < 6; i++) { wrmsr(MCI_STATUS + (i * 4), msr); } enable_cache(); /* Enable the local cpu apics */ setup_lapic(); /* Set the processor name string */ // init_processor_name(); #if CONFIG_LOGICAL_CPUS siblings = cpuid_ecx(0x80000008) & 0xff; if (siblings > 0) { msr = rdmsr_amd(CPU_ID_FEATURES_MSR); msr.lo |= 1 << 28; wrmsr_amd(CPU_ID_FEATURES_MSR, msr); msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR); msr.hi |= 1 << (33 - 32); wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr); } printk(BIOS_DEBUG, "siblings = %02d, ", siblings); #endif /* DisableCf8ExtCfg */ msr = rdmsr(NB_CFG_MSR); msr.hi &= ~(1 << (46 - 32)); wrmsr(NB_CFG_MSR, msr); /* Write protect SMM space with SMMLOCK. */ msr = rdmsr(HWCR_MSR); msr.lo |= (1 << 0); wrmsr(HWCR_MSR, msr); }
static u32 get_core_num_in_bsp(u32 nodeid) { u32 dword; dword = pci_read_config32(NODE_PCI(nodeid, 3), 0xe8); dword >>= 12; /* Bit 15 is CmpCap[2] since Revision D. */ if ((cpuid_ecx(0x80000008) & 0xff) > 3) dword = ((dword & 8) >> 1) | (dword & 3); else
static int cpu_has_effective_freq() { #if defined(__i386__) || defined(__x86_64__) /* largest base level */ if (cpuid_eax(0) < 6) return 0; return cpuid_ecx(6) & 0x1; #else return 0; #endif }
void intel_model_2065x_finalize_smm(void) { /* Lock C-State MSR */ msr_set_bit(MSR_PMG_CST_CONFIG_CONTROL, 15); /* Lock AES-NI only if supported */ if (cpuid_ecx(1) & (1 << 25)) msr_set_bit(MSR_FEATURE_CONFIG, 0); /* Lock TM interupts - route thermal events to all processors */ msr_set_bit(MSR_MISC_PWR_MGMT, 22); /* Lock memory configuration to protect SMM */ msr_set_bit(MSR_LT_LOCK_MEMORY, 0); }
static void set_energy_perf_bias(u8 policy) { msr_t msr; int ecx; /* Determine if energy efficient policy is supported. */ ecx = cpuid_ecx(0x6); if (!(ecx & (1 << 3))) return; /* Energy Policy is bits 3:0 */ msr = rdmsr(IA32_ENERGY_PERF_BIAS); msr.lo &= ~0xf; msr.lo |= policy & 0xf; wrmsr(IA32_ENERGY_PERF_BIAS, msr); }
static u32 get_core_num_in_bsp(u32 nodeid) { u32 dword; if (is_fam15h()) { /* Family 15h moved CmpCap to F5x84 [7:0] */ dword = pci_read_config32(NODE_PCI(nodeid, 5), 0x84); dword &= 0xff; } else { dword = pci_read_config32(NODE_PCI(nodeid, 3), 0xe8); dword >>= 12; /* Bit 15 is CmpCap[2] since Revision D. */ if ((cpuid_ecx(0x80000008) & 0xff) > 3) dword = ((dword & 8) >> 1) | (dword & 3); else dword &= 3; }
static void feature_detect(void *info) { struct cpufreq_policy *policy = info; unsigned int ecx, edx; ecx = cpuid_ecx(6); if (ecx & CPUID_6_ECX_APERFMPERF_CAPABILITY) { policy->aperf_mperf = 1; powernow_cpufreq_driver.getavg = get_measured_perf; } edx = cpuid_edx(CPUID_FREQ_VOLT_CAPABILITIES); if ((edx & CPB_CAPABLE) == CPB_CAPABLE) { policy->turbo = CPUFREQ_TURBO_ENABLED; if (cpufreq_verbose) printk(XENLOG_INFO "CPU%u: Core Boost/Turbo detected and enabled\n", smp_processor_id()); } }
static u8 cpu_core_number(void) { return (cpuid_ecx(0x80000008) & 0xFF) + 1; }
static void model_15_init(device_t dev) { printk(BIOS_DEBUG, "Model 15 Init.\n"); u8 i; msr_t msr; int msrno; unsigned int cpu_idx; #if IS_ENABLED(CONFIG_LOGICAL_CPUS) u32 siblings; #endif //x86_enable_cache(); //amd_setup_mtrrs(); //x86_mtrr_check(); disable_cache (); /* Enable access to AMD RdDram and WrDram extension bits */ msr = rdmsr(SYSCFG_MSR); msr.lo |= SYSCFG_MSR_MtrrFixDramModEn; msr.lo &= ~SYSCFG_MSR_MtrrFixDramEn; wrmsr(SYSCFG_MSR, msr); // BSP: make a0000-bffff UC, c0000-fffff WB, same as OntarioApMtrrSettingsList for APs msr.lo = msr.hi = 0; wrmsr (0x259, msr); msr.lo = msr.hi = 0x1e1e1e1e; wrmsr(0x250, msr); wrmsr(0x258, msr); for (msrno = 0x268; msrno <= 0x26f; msrno++) wrmsr (msrno, msr); msr = rdmsr(SYSCFG_MSR); msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; msr.lo |= SYSCFG_MSR_MtrrFixDramEn; wrmsr(SYSCFG_MSR, msr); if (acpi_is_wakeup()) restore_mtrr(); x86_mtrr_check(); x86_enable_cache(); /* zero the machine check error status registers */ msr.lo = 0; msr.hi = 0; for (i = 0; i < 6; i++) { wrmsr(MCI_STATUS + (i * 4), msr); } /* Enable the local cpu apics */ setup_lapic(); #if IS_ENABLED(CONFIG_LOGICAL_CPUS) siblings = cpuid_ecx(0x80000008) & 0xff; if (siblings > 0) { msr = rdmsr_amd(CPU_ID_FEATURES_MSR); msr.lo |= 1 << 28; wrmsr_amd(CPU_ID_FEATURES_MSR, msr); msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR); msr.hi |= 1 << (33 - 32); wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr); } printk(BIOS_DEBUG, "siblings = %02d, ", siblings); #endif /* DisableCf8ExtCfg */ msr = rdmsr(NB_CFG_MSR); msr.hi &= ~(1 << (46 - 32)); wrmsr(NB_CFG_MSR, msr); if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) { cpu_idx = cpu_info()->index; printk(BIOS_INFO, "Initializing SMM for CPU %u\n", cpu_idx); /* Set SMM base address for this CPU */ msr = rdmsr(MSR_SMM_BASE); msr.lo = SMM_BASE - (cpu_idx * 0x400); wrmsr(MSR_SMM_BASE, msr); /* Enable the SMM memory window */ msr = rdmsr(MSR_SMM_MASK); msr.lo |= (1 << 0); /* Enable ASEG SMRAM Range */ wrmsr(MSR_SMM_MASK, msr); } /* Write protect SMM space with SMMLOCK. */ msr = rdmsr(HWCR_MSR); msr.lo |= (1 << 0); wrmsr(HWCR_MSR, msr); }
static void model_15_init(device_t dev) { printk(BIOS_DEBUG, "Model 15 Init.\n"); u8 i; msr_t msr; int msrno; #if CONFIG_LOGICAL_CPUS u32 siblings; #endif disable_cache(); /* Enable access to AMD RdDram and WrDram extension bits */ msr = rdmsr(SYSCFG_MSR); msr.lo |= SYSCFG_MSR_MtrrFixDramModEn; msr.lo &= ~SYSCFG_MSR_MtrrFixDramEn; wrmsr(SYSCFG_MSR, msr); // BSP: make a0000-bffff UC, c0000-fffff WB msr.lo = msr.hi = 0; wrmsr(0x259, msr); msr.lo = msr.hi = 0x1e1e1e1e; wrmsr(0x250, msr); wrmsr(0x258, msr); for (msrno = 0x268; msrno <= 0x26f; msrno++) wrmsr(msrno, msr); msr = rdmsr(SYSCFG_MSR); msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; msr.lo |= SYSCFG_MSR_MtrrFixDramEn; wrmsr(SYSCFG_MSR, msr); if (acpi_is_wakeup()) restore_mtrr(); x86_mtrr_check(); x86_enable_cache(); /* zero the machine check error status registers */ msr.lo = 0; msr.hi = 0; for (i = 0; i < 6; i++) wrmsr(MCI_STATUS + (i * 4), msr); /* Enable the local CPU APICs */ setup_lapic(); #if CONFIG_LOGICAL_CPUS siblings = cpuid_ecx(0x80000008) & 0xff; if (siblings > 0) { msr = rdmsr_amd(CPU_ID_FEATURES_MSR); msr.lo |= 1 << 28; wrmsr_amd(CPU_ID_FEATURES_MSR, msr); msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR); msr.hi |= 1 << (33 - 32); wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr); } printk(BIOS_DEBUG, "siblings = %02d, ", siblings); #endif PSPProgBar3Msr(NULL); /* DisableCf8ExtCfg */ msr = rdmsr(NB_CFG_MSR); msr.hi &= ~(1 << (46 - 32)); wrmsr(NB_CFG_MSR, msr); /* Write protect SMM space with SMMLOCK. */ msr = rdmsr(HWCR_MSR); msr.lo |= (1 << 0); wrmsr(HWCR_MSR, msr); }
int get_cpu_info(unsigned int cpu, struct cpupower_cpu_info *cpu_info) { FILE *fp; char value[64]; unsigned int proc, x; unsigned int unknown = 0xffffff; unsigned int cpuid_level, ext_cpuid_level; int ret = -EINVAL; cpu_info->vendor = X86_VENDOR_UNKNOWN; cpu_info->family = unknown; cpu_info->model = unknown; cpu_info->stepping = unknown; cpu_info->caps = 0; fp = fopen("/proc/cpuinfo", "r"); if (!fp) return -EIO; while (!feof(fp)) { if (!fgets(value, 64, fp)) continue; value[63 - 1] = '\0'; if (!strncmp(value, "processor\t: ", 12)) sscanf(value, "processor\t: %u", &proc); if (proc != cpu) continue; /* */ if (!strncmp(value, "vendor_id", 9)) { for (x = 1; x < X86_VENDOR_MAX; x++) { if (strstr(value, cpu_vendor_table[x])) cpu_info->vendor = x; } /* */ } else if (!strncmp(value, "cpu family\t: ", 13)) { sscanf(value, "cpu family\t: %u", &cpu_info->family); } else if (!strncmp(value, "model\t\t: ", 9)) { sscanf(value, "model\t\t: %u", &cpu_info->model); } else if (!strncmp(value, "stepping\t: ", 10)) { sscanf(value, "stepping\t: %u", &cpu_info->stepping); /* */ if (cpu_info->vendor == X86_VENDOR_UNKNOWN || cpu_info->family == unknown || cpu_info->model == unknown || cpu_info->stepping == unknown) { ret = -EINVAL; goto out; } ret = 0; goto out; } } ret = -ENODEV; out: fclose(fp); /* */ if (cpu_info->vendor != X86_VENDOR_AMD && cpu_info->vendor != X86_VENDOR_INTEL) return ret; cpuid_level = cpuid_eax(0); ext_cpuid_level = cpuid_eax(0x80000000); /* */ if (ext_cpuid_level >= 0x80000007 && (cpuid_edx(0x80000007) & (1 << 8))) cpu_info->caps |= CPUPOWER_CAP_INV_TSC; /* */ if (cpuid_level >= 6 && (cpuid_ecx(6) & 0x1)) cpu_info->caps |= CPUPOWER_CAP_APERF; /* */ if (cpu_info->vendor == X86_VENDOR_AMD) { if (ext_cpuid_level >= 0x80000007 && (cpuid_edx(0x80000007) & (1 << 9))) cpu_info->caps |= CPUPOWER_CAP_AMD_CBP; } if (cpu_info->vendor == X86_VENDOR_INTEL) { if (cpuid_level >= 6 && (cpuid_eax(6) & (1 << 1))) cpu_info->caps |= CPUPOWER_CAP_INTEL_IDA; } if (cpu_info->vendor == X86_VENDOR_INTEL) { /* */ if (cpuid_level >= 6 && (cpuid_ecx(6) & (1 << 3))) cpu_info->caps |= CPUPOWER_CAP_PERF_BIAS; /* */ if (cpu_info->family == 6) { switch (cpu_info->model) { case 0x1A: /* */ case 0x1E: /* */ case 0x1F: /* */ case 0x25: /* */ case 0x2C: /* */ cpu_info->caps |= CPUPOWER_CAP_HAS_TURBO_RATIO; case 0x2A: /* */ case 0x2D: /* */ cpu_info->caps |= CPUPOWER_CAP_HAS_TURBO_RATIO; cpu_info->caps |= CPUPOWER_CAP_IS_SNB; break; case 0x2E: /* */ case 0x2F: /* */ default: break; } } } /* */ return ret; }
static void model_16_init(struct device *dev) { printk(BIOS_DEBUG, "Model 16 Init.\n"); u8 i; msr_t msr; int num_banks; int msrno; #if IS_ENABLED(CONFIG_LOGICAL_CPUS) u32 siblings; #endif //x86_enable_cache(); //amd_setup_mtrrs(); //x86_mtrr_check(); disable_cache(); /* Enable access to AMD RdDram and WrDram extension bits */ msr = rdmsr(SYSCFG_MSR); msr.lo |= SYSCFG_MSR_MtrrFixDramModEn; msr.lo &= ~SYSCFG_MSR_MtrrFixDramEn; wrmsr(SYSCFG_MSR, msr); // BSP: make a0000-bffff UC, c0000-fffff WB, same as OntarioApMtrrSettingsList for APs msr.lo = msr.hi = 0; wrmsr(MTRR_FIX_16K_A0000, msr); msr.lo = msr.hi = 0x1e1e1e1e; wrmsr(MTRR_FIX_64K_00000, msr); wrmsr(MTRR_FIX_16K_80000, msr); for (msrno = MTRR_FIX_4K_C0000; msrno <= MTRR_FIX_4K_F8000; msrno++) wrmsr(msrno, msr); msr = rdmsr(SYSCFG_MSR); msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; msr.lo |= SYSCFG_MSR_MtrrFixDramEn; wrmsr(SYSCFG_MSR, msr); if (acpi_is_wakeup()) restore_mtrr(); x86_mtrr_check(); x86_enable_cache(); /* zero the machine check error status registers */ msr = rdmsr(IA32_MCG_CAP); num_banks = msr.lo & MCA_BANKS_MASK; msr.lo = 0; msr.hi = 0; for (i = 0; i < num_banks; i++) wrmsr(IA32_MC0_STATUS + (i * 4), msr); /* Enable the local CPU APICs */ setup_lapic(); #if IS_ENABLED(CONFIG_LOGICAL_CPUS) siblings = cpuid_ecx(0x80000008) & 0xff; if (siblings > 0) { msr = rdmsr_amd(CPU_ID_FEATURES_MSR); msr.lo |= 1 << 28; wrmsr_amd(CPU_ID_FEATURES_MSR, msr); msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR); msr.hi |= 1 << (33 - 32); wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr); } printk(BIOS_DEBUG, "siblings = %02d, ", siblings); #endif /* DisableCf8ExtCfg */ msr = rdmsr(NB_CFG_MSR); msr.hi &= ~(1 << (46 - 32)); wrmsr(NB_CFG_MSR, msr); /* Write protect SMM space with SMMLOCK. */ msr = rdmsr(HWCR_MSR); msr.lo |= (1 << 0); wrmsr(HWCR_MSR, msr); }
int init_processor_name(void) { /* variable names taken from fam10 revision guide for clarity */ u32 BrandId; /* CPUID Fn8000_0001_EBX */ u8 String1; /* BrandID[14:11] */ u8 String2; /* BrandID[3:0] */ u8 Model; /* BrandID[10:4] */ u8 Pg; /* BrandID[15] */ u8 PkgTyp; /* BrandID[31:28] */ u8 NC; /* CPUID Fn8000_0008_ECX */ const char *processor_name_string = unknown; char program_string[48]; u32 *p_program_string = (u32 *)program_string; msr_t msr; int i, j = 0, str2_checkNC = 1; const struct str_s *str, *str2; /* Find out which CPU brand it is */ BrandId = cpuid_ebx(0x80000001); String1 = (u8)((BrandId >> 11) & 0x0F); String2 = (u8)((BrandId >> 0) & 0x0F); Model = (u8)((BrandId >> 4) & 0x7F); Pg = (u8)((BrandId >> 15) & 0x01); PkgTyp = (u8)((BrandId >> 28) & 0x0F); NC = (u8)(cpuid_ecx(0x80000008) & 0xFF); /* null the string */ memset(program_string, 0, sizeof(program_string)); if (!Model) { processor_name_string = Pg ? thermal : sample; goto done; } switch (PkgTyp) { case 0: /* F1207 */ str = String1_socket_F; str2 = String2_socket_F; str2_checkNC = 0; break; case 1: /* AM2 */ str = String1_socket_AM2; str2 = String2_socket_AM2; break; case 5: /* C32 */ str = String1_socket_C32; str2 = String2_socket_C32; break; default: goto done; } /* String1 */ for (i = 0; str[i].value; i++) { if ((str[i].Pg == Pg) && (str[i].NC == NC) && (str[i].String == String1)) { processor_name_string = str[i].value; break; } } if (!str[i].value) goto done; j = strcpymax(program_string, processor_name_string, sizeof(program_string)); /* Translate Model from 01-99 to ASCII and put it on the end. * Numbers less than 10 should include a leading zero, e.g., 09.*/ if (Model < 100 && j < sizeof(program_string) - 2) { program_string[j++] = (Model / 10) + '0'; program_string[j++] = (Model % 10) + '0'; } processor_name_string = unknown2; /* String 2 */ for(i = 0; str2[i].value; i++) { if ((str2[i].Pg == Pg) && ((str2[i].NC == NC) || !str2_checkNC) && (str2[i].String == String2)) { processor_name_string = str2[i].value; break; } } done: strcpymax(&program_string[j], processor_name_string, sizeof(program_string) - j); printk(BIOS_DEBUG, "CPU model: %s\n", program_string); for (i = 0; i < 6; i++) { msr.lo = p_program_string[(2 * i) + 0]; msr.hi = p_program_string[(2 * i) + 1]; wrmsr_amd(0xC0010030 + i, msr); } return 0; }
static void model_12_init(device_t dev) { printk(BIOS_DEBUG, "Model 12 Init.\n"); u8 i; msr_t msr; #if IS_ENABLED(CONFIG_LOGICAL_CPUS) u32 siblings; #endif // struct node_core_id id; // id = get_node_core_id(read_nb_cfg_54()); /* nb_cfg_54 can not be set */ // printk(BIOS_DEBUG, "nodeid = %02d, coreid = %02d\n", id.nodeid, id.coreid); /* Turn on caching if we haven't already */ x86_enable_cache(); amd_setup_mtrrs(); x86_mtrr_check(); disable_cache(); /* zero the machine check error status registers */ msr.lo = 0; msr.hi = 0; for (i = 0; i < 5; i++) { wrmsr(MCI_STATUS + (i * 4), msr); } enable_cache(); /* Enable the local CPU apics */ setup_lapic(); /* Set the processor name string */ // init_processor_name(); #if IS_ENABLED(CONFIG_LOGICAL_CPUS) siblings = cpuid_ecx(0x80000008) & 0xff; if (siblings > 0) { msr = rdmsr_amd(CPU_ID_FEATURES_MSR); msr.lo |= 1 << 28; wrmsr_amd(CPU_ID_FEATURES_MSR, msr); msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR); msr.hi |= 1 << (33 - 32); wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr); } printk(BIOS_DEBUG, "siblings = %02d, ", siblings); #endif /* DisableCf8ExtCfg */ msr = rdmsr(NB_CFG_MSR); msr.hi &= ~(1 << (46 - 32)); wrmsr(NB_CFG_MSR, msr); /* Write protect SMM space with SMMLOCK. */ msr = rdmsr(HWCR_MSR); msr.lo |= (1 << 0); wrmsr(HWCR_MSR, msr); }