int cs4340_phy_init(struct phy_device *phydev) { int timeout = 100; /* 100ms */ int reg_value; /* step1: BIST test */ phy_write(phydev, 0x00, VILLA_GLOBAL_MSEQCLKCTRL, 0x0004); phy_write(phydev, 0x00, VILLA_GLOBAL_LINE_SOFT_RESET, 0x0000); phy_write(phydev, 0x00, VILLA_GLOBAL_BIST_CONTROL, 0x0001); while (--timeout) { reg_value = phy_read(phydev, 0x00, VILLA_GLOBAL_BIST_STATUS); if (reg_value & mseq_edc_bist_done) { if (0 == (reg_value & mseq_edc_bist_fail)) break; } udelay(1000); } if (!timeout) { printf("%s BIST mseq_edc_bist_done timeout!\n", __func__); return -1; } /* setp2: upload ucode */ cs4340_upload_firmware(phydev); reg_value = phy_read(phydev, 0x00, VILLA_GLOBAL_DWNLD_CHECKSUM_STATUS); if (reg_value) { debug("%s checksum status failed.\n", __func__); return -1; } return 0; }
int cs4340_phy_init(struct phy_device *phydev) { #ifndef CORTINA_NO_FW_UPLOAD int timeout = 100; /* 100ms */ #endif int reg_value; /* * Cortina phy has provision to store * phy firmware in attached dedicated EEPROM. * Boards designed with EEPROM attached to Cortina * does not require FW upload. */ #ifndef CORTINA_NO_FW_UPLOAD /* step1: BIST test */ phy_write(phydev, 0x00, VILLA_GLOBAL_MSEQCLKCTRL, 0x0004); phy_write(phydev, 0x00, VILLA_GLOBAL_LINE_SOFT_RESET, 0x0000); phy_write(phydev, 0x00, VILLA_GLOBAL_BIST_CONTROL, 0x0001); while (--timeout) { reg_value = phy_read(phydev, 0x00, VILLA_GLOBAL_BIST_STATUS); if (reg_value & mseq_edc_bist_done) { if (0 == (reg_value & mseq_edc_bist_fail)) break; } udelay(1000); } if (!timeout) { printf("%s BIST mseq_edc_bist_done timeout!\n", __func__); return -1; } /* setp2: upload ucode */ cs4340_upload_firmware(phydev); #endif reg_value = phy_read(phydev, 0x00, VILLA_GLOBAL_DWNLD_CHECKSUM_STATUS); if (reg_value) { debug("%s checksum status failed.\n", __func__); return -1; } return 0; }