/* * omap4iss_csi2_isr - CSI2 interrupt handling. * * Return -EIO on Transmission error */ int omap4iss_csi2_isr(struct iss_csi2_device *csi2) { u32 csi2_irqstatus, cpxio1_irqstatus; struct iss_device *iss = csi2->iss; int retval = 0; if (!csi2->available) return -ENODEV; csi2_irqstatus = readl(csi2->regs1 + CSI2_IRQSTATUS); writel(csi2_irqstatus, csi2->regs1 + CSI2_IRQSTATUS); /* Failure Cases */ if (csi2_irqstatus & CSI2_IRQ_COMPLEXIO_ERR) { cpxio1_irqstatus = readl(csi2->regs1 + CSI2_COMPLEXIO_IRQSTATUS); writel(cpxio1_irqstatus, csi2->regs1 + CSI2_COMPLEXIO_IRQSTATUS); dev_dbg(iss->dev, "CSI2: ComplexIO Error IRQ " "%x\n", cpxio1_irqstatus); retval = -EIO; } if (csi2_irqstatus & (CSI2_IRQ_OCP_ERR | CSI2_IRQ_SHORT_PACKET | CSI2_IRQ_ECC_NO_CORRECTION | CSI2_IRQ_COMPLEXIO_ERR | CSI2_IRQ_FIFO_OVF)) { dev_dbg(iss->dev, "CSI2 Err:" " OCP:%d," " Short_pack:%d," " ECC:%d," " CPXIO:%d," " FIFO_OVF:%d," "\n", (csi2_irqstatus & CSI2_IRQ_OCP_ERR) ? 1 : 0, (csi2_irqstatus & CSI2_IRQ_SHORT_PACKET) ? 1 : 0, (csi2_irqstatus & CSI2_IRQ_ECC_NO_CORRECTION) ? 1 : 0, (csi2_irqstatus & CSI2_IRQ_COMPLEXIO_ERR) ? 1 : 0, (csi2_irqstatus & CSI2_IRQ_FIFO_OVF) ? 1 : 0); retval = -EIO; } if (omap4iss_module_sync_is_stopping(&csi2->wait, &csi2->stopping)) return 0; /* Successful cases */ if (csi2_irqstatus & CSI2_IRQ_CONTEXT0) csi2_isr_ctx(csi2, &csi2->contexts[0]); if (csi2_irqstatus & CSI2_IRQ_ECC_CORRECTION) dev_dbg(iss->dev, "CSI2: ECC correction done\n"); return retval; }
/* * omap3isp_csi2_isr - CSI2 interrupt handling. */ void omap3isp_csi2_isr(struct isp_csi2_device *csi2) { struct isp_pipeline *pipe = to_isp_pipeline(&csi2->subdev.entity); u32 csi2_irqstatus, cpxio1_irqstatus; struct isp_device *isp = csi2->isp; if (!csi2->available) return; csi2_irqstatus = isp_reg_readl(isp, csi2->regs1, ISPCSI2_IRQSTATUS); isp_reg_writel(isp, csi2_irqstatus, csi2->regs1, ISPCSI2_IRQSTATUS); /* Failure Cases */ if (csi2_irqstatus & ISPCSI2_IRQSTATUS_COMPLEXIO1_ERR_IRQ) { cpxio1_irqstatus = isp_reg_readl(isp, csi2->regs1, ISPCSI2_PHY_IRQSTATUS); isp_reg_writel(isp, cpxio1_irqstatus, csi2->regs1, ISPCSI2_PHY_IRQSTATUS); dev_dbg(isp->dev, "CSI2: ComplexIO Error IRQ " "%x\n", cpxio1_irqstatus); pipe->error = true; } if (csi2_irqstatus & (ISPCSI2_IRQSTATUS_OCP_ERR_IRQ | ISPCSI2_IRQSTATUS_SHORT_PACKET_IRQ | ISPCSI2_IRQSTATUS_ECC_NO_CORRECTION_IRQ | ISPCSI2_IRQSTATUS_COMPLEXIO2_ERR_IRQ | ISPCSI2_IRQSTATUS_FIFO_OVF_IRQ)) { dev_dbg(isp->dev, "CSI2 Err:" " OCP:%d," " Short_pack:%d," " ECC:%d," " CPXIO2:%d," " FIFO_OVF:%d," "\n", (csi2_irqstatus & ISPCSI2_IRQSTATUS_OCP_ERR_IRQ) ? 1 : 0, (csi2_irqstatus & ISPCSI2_IRQSTATUS_SHORT_PACKET_IRQ) ? 1 : 0, (csi2_irqstatus & ISPCSI2_IRQSTATUS_ECC_NO_CORRECTION_IRQ) ? 1 : 0, (csi2_irqstatus & ISPCSI2_IRQSTATUS_COMPLEXIO2_ERR_IRQ) ? 1 : 0, (csi2_irqstatus & ISPCSI2_IRQSTATUS_FIFO_OVF_IRQ) ? 1 : 0); pipe->error = true; } if (omap3isp_module_sync_is_stopping(&csi2->wait, &csi2->stopping)) return; /* Successful cases */ if (csi2_irqstatus & ISPCSI2_IRQSTATUS_CONTEXT(0)) csi2_isr_ctx(csi2, &csi2->contexts[0]); if (csi2_irqstatus & ISPCSI2_IRQSTATUS_ECC_CORRECTION_IRQ) dev_dbg(isp->dev, "CSI2: ECC correction done\n"); }
/* * omap4iss_csi2_isr - CSI2 interrupt handling. */ void omap4iss_csi2_isr(struct iss_csi2_device *csi2) { struct iss_pipeline *pipe = to_iss_pipeline(&csi2->subdev.entity); u32 csi2_irqstatus, cpxio1_irqstatus; struct iss_device *iss = csi2->iss; if (!csi2->available) return; csi2_irqstatus = iss_reg_read(csi2->iss, csi2->regs1, CSI2_IRQSTATUS); iss_reg_write(csi2->iss, csi2->regs1, CSI2_IRQSTATUS, csi2_irqstatus); /* Failure Cases */ if (csi2_irqstatus & CSI2_IRQ_COMPLEXIO_ERR) { cpxio1_irqstatus = iss_reg_read(csi2->iss, csi2->regs1, CSI2_COMPLEXIO_IRQSTATUS); iss_reg_write(csi2->iss, csi2->regs1, CSI2_COMPLEXIO_IRQSTATUS, cpxio1_irqstatus); dev_dbg(iss->dev, "CSI2: ComplexIO Error IRQ %x\n", cpxio1_irqstatus); pipe->error = true; } if (csi2_irqstatus & (CSI2_IRQ_OCP_ERR | CSI2_IRQ_SHORT_PACKET | CSI2_IRQ_ECC_NO_CORRECTION | CSI2_IRQ_COMPLEXIO_ERR | CSI2_IRQ_FIFO_OVF)) { dev_dbg(iss->dev, "CSI2 Err: OCP:%d SHORT:%d ECC:%d CPXIO:%d OVF:%d\n", csi2_irqstatus & CSI2_IRQ_OCP_ERR ? 1 : 0, csi2_irqstatus & CSI2_IRQ_SHORT_PACKET ? 1 : 0, csi2_irqstatus & CSI2_IRQ_ECC_NO_CORRECTION ? 1 : 0, csi2_irqstatus & CSI2_IRQ_COMPLEXIO_ERR ? 1 : 0, csi2_irqstatus & CSI2_IRQ_FIFO_OVF ? 1 : 0); pipe->error = true; } if (omap4iss_module_sync_is_stopping(&csi2->wait, &csi2->stopping)) return; /* Successful cases */ if (csi2_irqstatus & CSI2_IRQ_CONTEXT0) csi2_isr_ctx(csi2, &csi2->contexts[0]); if (csi2_irqstatus & CSI2_IRQ_ECC_CORRECTION) dev_dbg(iss->dev, "CSI2: ECC correction done\n"); }