static void dphy_cfg_start(void) { csi_core_write_part(PHY_TST_CRTL1, 0, PHY_TESTEN, 1); //phy_testen = 0 udelay(1); csi_core_write_part(PHY_TST_CRTL0,1, PHY_TESTCLK, 1); //phy_testclk = 1 udelay(1); }
int csi_phy_stop(unsigned int id) { ISP_PRINT(ISP_INFO,"csi_phy_stop being called \n"); /*reset phy*/ csi_core_write_part(PHY_SHUTDOWNZ, 0, 0, 1); csi_core_write_part(DPHY_RSTZ, 0, 0, 1); csi_core_write_part(CSI2_RESETN, 0, 0, 1); return 0; }
static void dphy_cfg_done(void) { csi_core_write_part(PHY_TST_CRTL1, 0, PHY_TESTEN, 1); //phy_testen = 0 udelay(1); csi_core_write_part(PHY_TST_CRTL0,1, PHY_TESTCLK, 1); //phy_testclk = 1 udelay(1); csi_core_write_part(PHY_TST_CRTL1, 0, PHY_TESTDIN, PHY_TESTDIN_W);//phy_testdin udelay(1); csi_core_write_part(PHY_TST_CRTL1, 1, PHY_TESTEN, 1);//phy_testen = 1 udelay(1); csi_core_write_part(PHY_TST_CRTL0, 0, PHY_TESTCLK, 1);//phy_testclk = 0 udelay(1); }
static void dphy_init_common(u32 bps_per_lane, u32 phy_id, u32 rx_mode) { u8 temp = 0; struct csi_pclk_cfg csi_pclk_cfg_val = {0, 0, 0, 0}; csi_core_write_part(PHY_SHUTDOWNZ, 0, 0, 1); csi_core_write_part(DPHY_RSTZ, 0, 0, 1); csi_core_write_part(PHY_TST_CRTL0, 1, PHY_TESTCLR, 1); udelay(1); csi_core_write_part(PHY_TST_CRTL0, 0, PHY_TESTCLR, 1); udelay(1); dphy_cfg_start(); #if defined(CONFIG_MACH_SP7720EA) #if defined(CONFIG_SC_FPGA) sci_glb_write(SPRD_GPIO_BASE + 0x0008, 0xd, -1UL); dphy_write(0x30, 0xc0, &temp); #endif dphy_write(0x37, 0x03, &temp); //LOG_DEBUG2 ("%04x default reg value: %04x\r\n", 0x37, temp); dphy_write(0x47, 0x03, &temp); //LOG_DEBUG2 ("%04x default reg value: %04x\r\n", 0x47, temp); dphy_write(0x57, 0x03, &temp); //LOG_DEBUG2 ("%04x default reg value: %04x\r\n", 0x57, temp); dphy_write(0x67, 0x03, &temp); dphy_write(0x77, 0x03, &temp); #else csi_get_pclk_cfg(bps_per_lane, &csi_pclk_cfg_val); #if IS_ENABLED(VERSION3L) || IS_ENABLED(VERSION3T) || IS_ENABLED(VERSION3D) if (0x03 == phy_id) { if (0x00 == rx_mode) { dphy_write(0x34, 0x14, &temp); } else { dphy_write(0x34, 0xA0, &temp); } } else { dphy_write(0x34, 0x14, &temp); } #else dphy_write(0x34, 0x14, &temp); #endif dphy_write(0x44, (((csi_pclk_cfg_val.hsfreqrange & 0x3F) << 1) & 0x7E), &temp); dphy_write(0x75, (0x80 | (csi_pclk_cfg_val.hsrxthssettle & 0x7F)), &temp); dphy_write(0x54, 0x14, &temp); dphy_write(0x64, 0x14, &temp); dphy_write(0x74, 0x14, &temp); #endif dphy_cfg_done(); }
u8 csi_unregister_line_event(u8 offset) { csi_registers_t reg_offset = 0; LOG_TRACE(); if (offset > 8) { return ERR_OUT_OF_BOUND; } reg_offset = ((offset / 4) == 1) ? DATA_IDS_2: DATA_IDS_1; return csi_core_write_part(reg_offset, 0x00, (offset * 8), 8); }
u8 csi_reset_controller() { /* active low - bit 0 */ int retVal = 0xffff; retVal = csi_core_write_part(CSI2_RESETN, 0, 0, 1); switch (retVal) { case SUCCESS: return csi_core_write_part(CSI2_RESETN, 1, 0, 1); break; case ERR_NOT_INIT: LOG_ERROR("Driver not initialized"); return retVal; break; default: LOG_ERROR("Undefined error"); return ERR_UNDEFINED; break; } }
u8 csi_register_line_event(u8 virtual_channel_no, csi_data_type_t data_type, u8 offset) { u8 id = 0; csi_registers_t reg_offset = 0; LOG_TRACE(); if ((virtual_channel_no > 4) || (offset > 8)) { return ERR_OUT_OF_BOUND; } id = (virtual_channel_no << 6) | data_type; reg_offset = ((offset / 4) == 1) ? DATA_IDS_2: DATA_IDS_1; return csi_core_write_part(reg_offset, id, (offset * 8), 8); }
static void csi_phy_configure(void) { unsigned char data[4]; csi_core_write_part(PHY_TST_CTRL0, 1, 0, 1); // udelay(5); csi_core_write_part(PHY_TST_CTRL0, 0, 0, 1); mipi_csih_dphy_test_data_in(0); mipi_csih_dphy_test_en(0); mipi_csih_dphy_test_clock(0); data[0]=0x00; //data[0]=0x06; /*448Mbps*/ //data[0]=0x13; mipi_csih_dphy_write(0x44,data, 1); data[0]=0x1e; mipi_csih_dphy_write(0xb0,data, 1); data[0]=0x1; mipi_csih_dphy_write(0xb1,data, 1); }
static void dphy_init_common(u32 pclk, u32 phy_id, u32 rx_mode) { u8 temp = 0; struct csi_pclk_cfg csi_pclk_cfg_val = {0, 0, 0, 0}; csi_core_write_part(PHY_SHUTDOWNZ, 0, 0, 1); csi_core_write_part(DPHY_RSTZ, 0, 0, 1); csi_core_write_part(PHY_TST_CRTL0, 1, PHY_TESTCLR, 1); udelay(1); csi_core_write_part(PHY_TST_CRTL0, 0, PHY_TESTCLR, 1); udelay(1); dphy_cfg_start(); csi_get_pclk_cfg(pclk, &csi_pclk_cfg_val); #if defined(CONFIG_ARCH_SCX30G) if (0x03 == phy_id) { if (0x00 == rx_mode) { dphy_write(0x34, 0xA0, &temp); } else { dphy_write(0x34, 0x14, &temp); } } else { dphy_write(0x34, 0x14, &temp); } #else dphy_write(0x34, 0x14, &temp); #endif dphy_write(0x44, (((csi_pclk_cfg_val.hsfreqrange & 0x3F) << 1) & 0x7E), &temp); dphy_write(0x75, (0x80 | (csi_pclk_cfg_val.hsrxthssettle & 0x7F)), &temp); dphy_write(0x54, 0x14, &temp); dphy_write(0x64, 0x14, &temp); dphy_write(0x74, 0x14, &temp); dphy_cfg_done(); }
static void dphy_write(u8 test_code, u8 test_data, u8* test_out) { u32 temp = 0xffffff00; csi_core_write_part(PHY_TST_CRTL1, 0, PHY_TESTEN, 1); //phy_testen = 0 udelay(1); csi_core_write_part(PHY_TST_CRTL0,1, PHY_TESTCLK, 1); //phy_testclk = 1 udelay(1); csi_core_write_part(PHY_TST_CRTL1, test_code, PHY_TESTDIN, PHY_TESTDIN_W); //phy_testdin udelay(1); csi_core_write_part(PHY_TST_CRTL1, 1, PHY_TESTEN, 1);//phy_testen = 1 udelay(1); csi_core_write_part(PHY_TST_CRTL0, 0, PHY_TESTCLK, 1);//phy_testclk = 0 udelay(1); temp = csi_core_read_part(PHY_TST_CRTL1, PHY_TESTDOUT,PHY_TESTDOUT_W); *test_out = (u8)temp; udelay(1); csi_core_write_part(PHY_TST_CRTL1, 0, PHY_TESTEN, 1); //phy_testen = 0 udelay(1); csi_core_write_part(PHY_TST_CRTL1, test_data, PHY_TESTDIN, PHY_TESTDIN_W);//phy_testdin udelay(1); csi_core_write_part(PHY_TST_CRTL0,1, PHY_TESTCLK, 1);//phy_testclk = 1 udelay(1); }
int csi_phy_start(unsigned int id, unsigned int freq, unsigned int lans) { int retries = 30; int i; //ISP_PRINT(ISP_INFO,"csi_phy_start being called\n"); csi_set_on_lanes(lans); /*reset phy*/ csi_core_write_part(PHY_SHUTDOWNZ, 0, 0, 1); csi_core_write_part(DPHY_RSTZ, 0, 0, 1); csi_core_write_part(CSI2_RESETN, 0, 0, 1); csi_phy_configure(); /*active phy*/ //udelay(10); csi_core_write_part(PHY_SHUTDOWNZ, 1, 0, 1); //udelay(10); csi_core_write_part(DPHY_RSTZ, 1, 0, 1); //udelay(10); csi_core_write_part(CSI2_RESETN, 1, 0, 1); /* MASK all interrupts */ csi_event_disable(0xffffffff, 1); csi_event_disable(0xffffffff, 2); /* wait for phy ready */ for (i = 0; i < retries; i++) { if (csi_phy_ready(id)) break; udelay(2); } //ISP_PRINT(ISP_INFO,"%s:%d\n",__func__, i); if (i >= retries) { //ISP_PRINT(ISP_ERROR,"CSI PHY is not ready\n"); return -1; } //ISP_PRINT(ISP_INFO,"csi_phy_start ok!\n"); // mdelay(200); return 0; }
u8 csi_payload_bypass(u8 on) { return csi_core_write_part(PHY_STATE, on? 1: 0, 11, 1); }
u8 csi_shut_down_phy(u8 shutdown) { LOG_DEBUG2("shutdown", shutdown); /* active low - bit 0 */ return csi_core_write_part(PHY_SHUTDOWNZ, shutdown? 0: 1, 0, 1); }
u8 csi_set_on_lanes(u8 lanes) { return csi_core_write_part(N_LANES, (lanes - 1), 0, 2); }
int csi_phy_release(void) { csi_core_write_part(CSI2_RESETN, 0, 0, 1); csi_core_write_part(CSI2_RESETN, 1, 0, 1); return 0; }
static void mipi_csih_dphy_test_clock(int value) { csi_core_write_part(PHY_TST_CTRL0, value, 1, 1); }
static void mipi_csih_dphy_test_en(unsigned char on_falling_edge) { csi_core_write_part(PHY_TST_CTRL1, on_falling_edge, 16, 1); }
unsigned char csi_set_on_lanes(unsigned char lanes) { //ISP_PRINT(ISP_INFO,"%s:----------> lane num: %d\n", __func__, lanes); return csi_core_write_part(N_LANES, (lanes - 1), 0, 2); }