static void dmafetch_set_fmt(struct mmp_overlay *overlay) { u32 tmp; struct mmp_path *path = overlay->path; tmp = readl_relaxed(ctrl_regs(path) + dma_ctrl(0, path->id)); tmp &= ~dma_mask(overlay_is_vid(overlay)); tmp |= fmt_to_reg(overlay, overlay->win.pix_fmt); writel_relaxed(tmp, ctrl_regs(path) + dma_ctrl(0, path->id)); }
static void path_enabledisable(struct mmp_path *path, int on) { u32 tmp; mutex_lock(&path->access_ok); tmp = readl_relaxed(ctrl_regs(path) + LCD_SCLK(path)); if (on) tmp &= ~SCLK_DISABLE; else tmp |= SCLK_DISABLE; writel_relaxed(tmp, ctrl_regs(path) + LCD_SCLK(path)); mutex_unlock(&path->access_ok); }
static void path_set_default(struct mmp_path *path) { struct lcd_regs *regs = path_regs(path); u32 dma_ctrl1, mask, tmp, path_config; path_config = path_to_path_plat(path)->path_config; /* Configure IOPAD: should be parallel only */ if (PATH_OUT_PARALLEL == path->output_type) { mask = CFG_IOPADMODE_MASK | CFG_BURST_MASK | CFG_BOUNDARY_MASK; tmp = readl_relaxed(ctrl_regs(path) + SPU_IOPAD_CONTROL); tmp &= ~mask; tmp |= path_config; writel_relaxed(tmp, ctrl_regs(path) + SPU_IOPAD_CONTROL); } /* Select path clock source */ tmp = readl_relaxed(ctrl_regs(path) + LCD_SCLK(path)); tmp &= ~SCLK_SRC_SEL_MASK; tmp |= path_config; writel_relaxed(tmp, ctrl_regs(path) + LCD_SCLK(path)); /* * Configure default bits: vsync triggers DMA, * power save enable, configure alpha registers to * display 100% graphics, and set pixel command. */ dma_ctrl1 = 0x2032ff81; dma_ctrl1 |= CFG_VSYNC_INV_MASK; writel_relaxed(dma_ctrl1, ctrl_regs(path) + dma_ctrl(1, path->id)); /* Configure default register values */ writel_relaxed(0x00000000, ®s->blank_color); writel_relaxed(0x00000000, ®s->g_1); writel_relaxed(0x00000000, ®s->g_start); /* * 1.enable multiple burst request in DMA AXI * bus arbiter for faster read if not tv path; * 2.enable horizontal smooth filter; */ if (PATH_PN == path->id) { mask = CFG_GRA_HSMOOTH_MASK | CFG_DMA_HSMOOTH_MASK | CFG_ARBFAST_ENA(1); tmp = readl_relaxed(ctrl_regs(path) + dma_ctrl(0, path->id)); tmp |= mask; writel_relaxed(tmp, ctrl_regs(path) + dma_ctrl(0, path->id)); } else if (PATH_TV == path->id) { mask = CFG_GRA_HSMOOTH_MASK | CFG_DMA_HSMOOTH_MASK | CFG_ARBFAST_ENA(1); tmp = readl_relaxed(ctrl_regs(path) + dma_ctrl(0, path->id)); tmp &= ~mask; tmp |= CFG_GRA_HSMOOTH_MASK | CFG_DMA_HSMOOTH_MASK; writel_relaxed(tmp, ctrl_regs(path) + dma_ctrl(0, path->id)); } }
static void dmafetch_onoff(struct mmp_overlay *overlay, int on) { u32 mask = overlay_is_vid(overlay) ? CFG_DMA_ENA_MASK : CFG_GRA_ENA_MASK; u32 enable = overlay_is_vid(overlay) ? CFG_DMA_ENA(1) : CFG_GRA_ENA(1); u32 tmp; struct mmp_path *path = overlay->path; mutex_lock(&overlay->access_ok); tmp = readl_relaxed(ctrl_regs(path) + dma_ctrl(0, path->id)); tmp &= ~mask; tmp |= (on ? enable : 0); writel(tmp, ctrl_regs(path) + dma_ctrl(0, path->id)); mutex_unlock(&overlay->access_ok); }
static void path_set_mode(struct mmp_path *path, struct mmp_mode *mode) { struct lcd_regs *regs = path_regs(path); u32 total_x, total_y, vsync_ctrl, tmp, sclk_src, sclk_div, link_config = path_to_path_plat(path)->link_config; /* FIXME: assert videomode supported */ memcpy(&path->mode, mode, sizeof(struct mmp_mode)); mutex_lock(&path->access_ok); /* polarity of timing signals */ tmp = readl_relaxed(ctrl_regs(path) + intf_ctrl(path->id)) & 0x1; tmp |= mode->vsync_invert ? 0x8 : 0; tmp |= mode->hsync_invert ? 0x4 : 0; tmp |= link_config & CFG_DUMBMODE_MASK; tmp |= CFG_DUMB_ENA(1); writel_relaxed(tmp, ctrl_regs(path) + intf_ctrl(path->id)); /* interface rb_swap setting */ tmp = readl_relaxed(ctrl_regs(path) + intf_rbswap_ctrl(path->id)) & (~(CFG_INTFRBSWAP_MASK)); tmp |= link_config & CFG_INTFRBSWAP_MASK; writel_relaxed(tmp, ctrl_regs(path) + intf_rbswap_ctrl(path->id)); writel_relaxed((mode->yres << 16) | mode->xres, ®s->screen_active); writel_relaxed((mode->left_margin << 16) | mode->right_margin, ®s->screen_h_porch); writel_relaxed((mode->upper_margin << 16) | mode->lower_margin, ®s->screen_v_porch); total_x = mode->xres + mode->left_margin + mode->right_margin + mode->hsync_len; total_y = mode->yres + mode->upper_margin + mode->lower_margin + mode->vsync_len; writel_relaxed((total_y << 16) | total_x, ®s->screen_size); /* vsync ctrl */ if (path->output_type == PATH_OUT_DSI) vsync_ctrl = 0x01330133; else vsync_ctrl = ((mode->xres + mode->right_margin) << 16) | (mode->xres + mode->right_margin); writel_relaxed(vsync_ctrl, ®s->vsync_ctrl); /* set pixclock div */ sclk_src = clk_get_rate(path_to_ctrl(path)->clk); sclk_div = sclk_src / mode->pixclock_freq; if (sclk_div * mode->pixclock_freq < sclk_src) sclk_div++; dev_info(path->dev, "%s sclk_src %d sclk_div 0x%x pclk %d\n", __func__, sclk_src, sclk_div, mode->pixclock_freq); tmp = readl_relaxed(ctrl_regs(path) + LCD_SCLK(path)); tmp &= ~CLK_INT_DIV_MASK; tmp |= sclk_div; writel_relaxed(tmp, ctrl_regs(path) + LCD_SCLK(path)); mutex_unlock(&path->access_ok); }