/* Page 101 (7-25) in the Family Manual */ static void dsp56k_reset(void *param) { if (param == NULL) { LINE_RESET = 1 ; /* Handle internal stuff */ dsp56k.interrupt_cycles = 0 ; /* Internal peripheral devices are reset, and pins revert to general I/O pins */ /* Modifier registers are set */ M0 = M1 = M2 = M3 = 0xffff ; /* BCR is set */ BCR = 0x43ff ; /* Stack pointer is cleared */ SP = 0x00 ; /* The docs say nothing about ufFLAG & seFLAG, but this should be right */ /* Documentation says 'MR' is setup, but it really means 'SR' is setup */ SR = 0x0300 ; /* Only the Interrupt mask bits of the Status Register are set upon reset */ OMR = 0x00 ; /* All is cleared, except for the IRQ lines below */ IPR = 0x00 ; dsp56k.repFlag = 0 ; /* Certainly not repeating to start */ dsp56k.repAddr = 0x0000 ; /* Reset the address too... */ /* Wait here in RESET state until the RESET interrupt is deasserted */ /* UINT64 waitLoop = 0 ; */ /* while(LINE_RESET) */ /* { */ /* waitLoop++ ; */ /* } */ /* Manipulate everything you need to for the ports (!! maybe these will be callbacks someday !!)... */ data_write_word_16le(0xffde, 0x43ff) ; /* Sets Port A Bus Control Register (BCR) to the really slow bootup mode... */ /* Also sets the Bus State status bit high (0x4xxx) */ data_write_word_16le(0xffc0, 0x0000) ; /* Sets Port B Control Register to general I/O */ data_write_word_16le(0xffc2, 0x0000) ; /* Sets Port B Data Direction Register as input */ data_write_word_16le(0xffc1, 0x0000) ; /* Sets Port C Control Register to general I/O */ data_write_word_16le(0xffc3, 0x0000) ; /* Sets Port C Data Direction Register as input */ /* Now that we're leaving, set ma, mb, and mc from MODA, MODB, and MODC lines */ /* I believe polygonet sets everyone to mode 0... The following reflects this... */ CLEAR_maFLAG() ; CLEAR_mbFLAG() ; /* switch bootup sequence based on chip operating mode */ switch((mbFLAG << 1) | maFLAG) { /* [Special Bootstrap 1] Bootstrap from an external byte-wide memory located at P:$c000 */ case 0x0: PC = 0x0000 ; /* 0x0030 ; // 0x0032 ; // 0x002e ; // 0x0000 ; // 0x002c ; */ break ; /* [Special Bootstrap 2] Bootstrap from the Host port or SSI0 */ case 0x1: PC = 0x0000 ; break ; /* [Normal Expanded] Internal PRAM enabled; External reset at P:$e000 */ case 0x2: PC = 0xe000 ; break ; /* [Development Expanded] Int. program memory disabled; Ext. reset at P:$0000 */ case 0x3: PC = 0x0000 ; break ; } } else { PC = *((UINT16*)param) ; } }
INLINE void DM_WRITE16(UINT16 address, UINT16 data) { data_write_word_16le(address << 1, data); }
// Page 101 (7-25) in the Family Manual static void dsp56k_reset(void) { if (dsp56k.config == NULL) { memory_set_opbase(PC); // Handle internal stuff dsp56k.interrupt_cycles = 0; // Internal peripheral devices are reset, and pins revert to general I/O pins // Modifier registers are set M0 = M1 = M2 = M3 = 0xffff; // BCR is set - the really slow bootup mode & the Bus State status bit high (0x4xxx) //BCR = 0x43ff; // Stack pointer is cleared SP = 0x00; // The docs say nothing about ufBIT & seBIT, but this should be right // Documentation says 'MR' is setup, but it really means 'SR' is setup SR = 0x0300; // Only the Interrupt mask bits of the Status Register are set upon reset // !!! GO THROUGH AND GET ALL THESE RIGHT SOMEDAY !!! HSR = 0x0000; SET_htdeBIT(); dsp56k_reset_HI(); OMR = 0x00; // All is cleared, except for the IRQ lines below IPR = 0x00; dsp56k.repFlag = 0; // Certainly not repeating to start dsp56k.repAddr = 0x0000; // Reset the address too... // Manipulate everything you need to for the ports (!! maybe these will be callbacks someday !!)... data_write_word_16le(0xffc0, 0x0000); // Sets Port B Control Register to general I/O data_write_word_16le(0xffc2, 0x0000); // Sets Port B Data Direction Register as input data_write_word_16le(0xffc1, 0x0000); // Sets Port C Control Register to general I/O data_write_word_16le(0xffc3, 0x0000); // Sets Port C Data Direction Register as input // Now that we're leaving, set ma, mb, and mc from MODA, MODB, and MODC lines // I believe polygonet sets everyone to mode 0... The following reflects this... CLEAR_maBIT(); CLEAR_mbBIT(); // switch bootup sequence based on chip operating mode switch((mbBIT << 1) | maBIT) { // [Special Bootstrap 1] Bootstrap from an external byte-wide memory located at P:$c000 case 0x0: PC = 0x0000; // 0x0030; // 0x0032; // 0x002e; // 0x0000; // 0x002c; break; // [Special Bootstrap 2] Bootstrap from the Host port or SSI0 case 0x1: PC = 0x0000; break; // [Normal Expanded] Internal PRAM enabled; External reset at P:$e000 case 0x2: PC = 0xe000; break; // [Development Expanded] Int. program memory disabled; Ext. reset at P:$0000 case 0x3: PC = 0x0000; break; } } else { PC = *((UINT16*)dsp56k.config); } }