C++ (Cpp) davinci_alloc_gc 예제들

예제 #1

파일: irq.c 프로젝트: CSCLOG/beaglebone

/* ARM Interrupt Controller Initialization */
void __init davinci_irq_init(void)
{
    unsigned i, j;
    const u8 *davinci_def_priorities = davinci_soc_info.intc_irq_prios;

    davinci_intc_type = DAVINCI_INTC_TYPE_AINTC;
    davinci_intc_base = ioremap(davinci_soc_info.intc_base, SZ_4K);
    if (WARN_ON(!davinci_intc_base))
        return;

    /* Clear all interrupt requests */
    davinci_irq_writel(~0x0, FIQ_REG0_OFFSET);
    davinci_irq_writel(~0x0, FIQ_REG1_OFFSET);
    davinci_irq_writel(~0x0, IRQ_REG0_OFFSET);
    davinci_irq_writel(~0x0, IRQ_REG1_OFFSET);

    /* Disable all interrupts */
    davinci_irq_writel(0x0, IRQ_ENT_REG0_OFFSET);
    davinci_irq_writel(0x0, IRQ_ENT_REG1_OFFSET);

    /* Interrupts disabled immediately, IRQ entry reflects all */
    davinci_irq_writel(0x0, IRQ_INCTL_REG_OFFSET);

    /* we don't use the hardware vector table, just its entry addresses */
    davinci_irq_writel(0, IRQ_EABASE_REG_OFFSET);

    /* Clear all interrupt requests */
    davinci_irq_writel(~0x0, FIQ_REG0_OFFSET);
    davinci_irq_writel(~0x0, FIQ_REG1_OFFSET);
    davinci_irq_writel(~0x0, IRQ_REG0_OFFSET);
    davinci_irq_writel(~0x0, IRQ_REG1_OFFSET);

    for (i = IRQ_INTPRI0_REG_OFFSET; i <= IRQ_INTPRI7_REG_OFFSET; i += 4) {
        u32		pri;

        for (j = 0, pri = 0; j < 32; j += 4, davinci_def_priorities++)
            pri |= (*davinci_def_priorities & 0x07) << j;
        davinci_irq_writel(pri, i);
    }

    for (i = 0, j = 0; i < davinci_soc_info.intc_irq_num; i += 32, j += 0x04)
        davinci_alloc_gc(davinci_intc_base + j, i, 32);

    irq_set_handler(IRQ_TINT1_TINT34, handle_level_irq);
}

예제 #2

파일: irq.c 프로젝트: Blackburn29/PsycoKernel

void __init davinci_irq_init(void)
{
	unsigned i, j;
	const u8 *davinci_def_priorities = davinci_soc_info.intc_irq_prios;

	davinci_intc_type = DAVINCI_INTC_TYPE_AINTC;
	davinci_intc_base = ioremap(davinci_soc_info.intc_base, SZ_4K);
	if (WARN_ON(!davinci_intc_base))
		return;

	
	davinci_irq_writel(~0x0, FIQ_REG0_OFFSET);
	davinci_irq_writel(~0x0, FIQ_REG1_OFFSET);
	davinci_irq_writel(~0x0, IRQ_REG0_OFFSET);
	davinci_irq_writel(~0x0, IRQ_REG1_OFFSET);

	
	davinci_irq_writel(0x0, IRQ_ENT_REG0_OFFSET);
	davinci_irq_writel(0x0, IRQ_ENT_REG1_OFFSET);

	
	davinci_irq_writel(0x0, IRQ_INCTL_REG_OFFSET);

	
	davinci_irq_writel(0, IRQ_EABASE_REG_OFFSET);

	
	davinci_irq_writel(~0x0, FIQ_REG0_OFFSET);
	davinci_irq_writel(~0x0, FIQ_REG1_OFFSET);
	davinci_irq_writel(~0x0, IRQ_REG0_OFFSET);
	davinci_irq_writel(~0x0, IRQ_REG1_OFFSET);

	for (i = IRQ_INTPRI0_REG_OFFSET; i <= IRQ_INTPRI7_REG_OFFSET; i += 4) {
		u32		pri;

		for (j = 0, pri = 0; j < 32; j += 4, davinci_def_priorities++)
			pri |= (*davinci_def_priorities & 0x07) << j;
		davinci_irq_writel(pri, i);
	}

	for (i = 0, j = 0; i < davinci_soc_info.intc_irq_num; i += 32, j += 0x04)
		davinci_alloc_gc(davinci_intc_base + j, i, 32);

	irq_set_handler(IRQ_TINT1_TINT34, handle_level_irq);
}