static void serialrom_write_bit(struct channel *channel, u32 bit)
{
unsigned long addr = channel->card->bootrom_addr;
u32 lastbit = -1;
bit &= 1;
if (bit != lastbit) {
dc_write(addr, SBE_2T3E3_21143_REG_BOOT_ROM_SERIAL_ROM_AND_MII_MANAGEMENT,
SBE_2T3E3_21143_VAL_WRITE_OPERATION |
SBE_2T3E3_21143_VAL_SERIAL_ROM_SELECT |
SBE_2T3E3_21143_VAL_SERIAL_ROM_CHIP_SELECT |
(bit << 2)); /* clock low */
lastbit = bit;
}
dc_write(addr, SBE_2T3E3_21143_REG_BOOT_ROM_SERIAL_ROM_AND_MII_MANAGEMENT,
SBE_2T3E3_21143_VAL_WRITE_OPERATION |
SBE_2T3E3_21143_VAL_SERIAL_ROM_SELECT |
SBE_2T3E3_21143_VAL_SERIAL_ROM_CLOCK |
SBE_2T3E3_21143_VAL_SERIAL_ROM_CHIP_SELECT |
(bit << 2)); /* clock high */
dc_write(addr, SBE_2T3E3_21143_REG_BOOT_ROM_SERIAL_ROM_AND_MII_MANAGEMENT,
SBE_2T3E3_21143_VAL_WRITE_OPERATION |
SBE_2T3E3_21143_VAL_SERIAL_ROM_SELECT |
SBE_2T3E3_21143_VAL_SERIAL_ROM_CHIP_SELECT |
(bit << 2)); /* clock low */
}
void MakeItRobotics::all_stop()
{
dc_write(DC_CMD_PWMA, 0);
dc_write(DC_CMD_PWMB, 0);
dc_write(DC_CMD_PWMC, 0);
dc_write(DC_CMD_PWMD, 0);
}
void MakeItRobotics::m4_action(int dir, int speed)
{
if (speed >= 255)
speed = 1;
else if(speed!=0)
speed = 256 - speed;
dc_write(DC_CMD_DIRD, dir ? FW : BW);
dc_write(DC_CMD_PWMD, speed);
}
void MakeItRobotics::turn_right(int speed)
{
if (speed >= 255)
speed = 1;
else if(speed!=0)
speed = 256 - speed;
dc_write(DC_CMD_DIRA, FW);
dc_write(DC_CMD_DIRB, BW);
dc_write(DC_CMD_PWMA, speed);
dc_write(DC_CMD_PWMB, speed);
}
void MakeItRobotics::go_backward(int speed)
{
if (speed >= 255)
speed = 1;
else if(speed!=0)
speed = 256 - speed;
dc_write(DC_CMD_DIRA, BW);
dc_write(DC_CMD_DIRB, BW);
dc_write(DC_CMD_PWMA, speed);
dc_write(DC_CMD_PWMB, speed);
}
main(int argc, char *argv[])
{
int fd;
time_t t, tt = 0;
off_t size, tsize = 0, n;
char *buf;
int count;
if(argc != 4) {
printf("Usage: %s <file> <buffersize> <count>\n", argv[0]);
exit(1);
}
count = atoi(argv[3]);
dc_setDebugLevel(2);
size = atoi(argv[2]);
buf = (char *)malloc(size);
fd = dc_creat(argv[1], 0644);
t = time(NULL);
while (count--) {
n = dc_write(fd, buf, size);
tsize += n;
printf("%d ", count);
}
tt = time(NULL) - t;
dc_close(fd);
printf(" Speed = %.2f\n", ((float) tsize / (float) tt)/(float)1024);
}
void dc_set_loopback(struct channel *sc, u32 mode)
{
u32 val;
switch (mode) {
case SBE_2T3E3_21143_VAL_LOOPBACK_OFF:
case SBE_2T3E3_21143_VAL_LOOPBACK_INTERNAL:
break;
default:
return;
}
/* select loopback mode */
val = dc_read(sc->addr, SBE_2T3E3_21143_REG_OPERATION_MODE) &
~SBE_2T3E3_21143_VAL_OPERATING_MODE;
val |= mode;
dc_write(sc->addr, SBE_2T3E3_21143_REG_OPERATION_MODE, val);
if (mode == SBE_2T3E3_21143_VAL_LOOPBACK_OFF)
dc_set_bits(sc->addr, SBE_2T3E3_21143_REG_OPERATION_MODE,
SBE_2T3E3_21143_VAL_FULL_DUPLEX_MODE);
else
dc_clear_bits(sc->addr, SBE_2T3E3_21143_REG_OPERATION_MODE,
SBE_2T3E3_21143_VAL_FULL_DUPLEX_MODE);
}
void dc_clear_descriptor_list(struct channel *sc)
{
u32 i;
/* clear CSR3 and CSR4 */
dc_write(sc->addr, SBE_2T3E3_21143_REG_RECEIVE_LIST_BASE_ADDRESS, 0);
dc_write(sc->addr, SBE_2T3E3_21143_REG_TRANSMIT_LIST_BASE_ADDRESS, 0);
/* free all data buffers on TX ring */
for (i = 0; i < SBE_2T3E3_TX_DESC_RING_SIZE; i++) {
if (sc->ether.tx_data[i] != NULL) {
dev_kfree_skb_any(sc->ether.tx_data[i]);
sc->ether.tx_data[i] = NULL;
}
}
}
void dc_set_output_port(struct channel *sc)
{
dc_clear_bits(sc->addr, SBE_2T3E3_21143_REG_OPERATION_MODE,
SBE_2T3E3_21143_VAL_PORT_SELECT);
dc_write(sc->addr, SBE_2T3E3_21143_REG_SIA_STATUS, 0x00000301);
dc_write(sc->addr, SBE_2T3E3_21143_REG_SIA_CONNECTIVITY, 0);
dc_write(sc->addr, SBE_2T3E3_21143_REG_SIA_TRANSMIT_AND_RECEIVE, 0);
dc_write(sc->addr, SBE_2T3E3_21143_REG_SIA_AND_GENERAL_PURPOSE_PORT, 0x08000011);
dc_set_bits(sc->addr, SBE_2T3E3_21143_REG_OPERATION_MODE,
SBE_2T3E3_21143_VAL_TRANSMIT_THRESHOLD_MODE_100Mbs |
SBE_2T3E3_21143_VAL_HEARTBEAT_DISABLE |
SBE_2T3E3_21143_VAL_PORT_SELECT |
SBE_2T3E3_21143_VAL_FULL_DUPLEX_MODE);
}
int
_tmain(int argc, const TCHAR **argv)
{
HDC screen;
screen = GetDC(NULL);
dc_dump(screen);
ReleaseDC(NULL, screen);
#if 0
HDC dc;
HBITMAP bmp, origin_bmp;
{
/*
HDC screen = GetDC(NULL);
const int w = GetSystemMetrics(SM_CXSCREEN);
const int h = GetSystemMetrics(SM_CYSCREEN);
dc = CreateCompatibleDC(screen);
bmp = CreateCompatibleBitmap(screen, w, h);
ReleaseDC(NULL, screen);
*/
}
origin_bmp = SelectObject(dc, bmp);
dc_shot(dc);
dc_write(dc);
DeleteObject(SelectObject(dc, origin_bmp));
DeleteDC(dc);
#endif
return 0;
}
void t3e3_reg_write(struct channel *sc, u32 *reg)
{
u32 i;
switch (reg[0]) {
case SBE_2T3E3_CHIP_21143:
dc_write(sc->addr, reg[1], reg[2]);
break;
case SBE_2T3E3_CHIP_CPLD:
for (i = 0; i < SBE_2T3E3_CPLD_REG_MAX; i++)
if (cpld_reg_map[i][sc->h.slot] == reg[1]) {
cpld_write(sc, i, reg[2]);
break;
}
break;
case SBE_2T3E3_CHIP_FRAMER:
for (i = 0; i < SBE_2T3E3_FRAMER_REG_MAX; i++)
if (t3e3_framer_reg_map[i] == reg[1]) {
exar7250_write(sc, i, reg[2]);
break;
}
break;
case SBE_2T3E3_CHIP_LIU:
for (i = 0; i < SBE_2T3E3_LIU_REG_MAX; i++)
if (t3e3_liu_reg_map[i] == reg[1]) {
exar7300_write(sc, i, reg[2]);
break;
}
break;
}
}
void dc_set_loopback(struct channel *sc, u32 mode)
{
u32 val;
switch (mode) {
case SBE_2T3E3_21143_VAL_LOOPBACK_OFF:
case SBE_2T3E3_21143_VAL_LOOPBACK_INTERNAL:
break;
default:
return;
}
#if 0
/* restart SIA */
dc_clear_bits(sc->addr, SBE_2T3E3_21143_REG_SIA_CONNECTIVITY,
SBE_2T3E3_21143_VAL_SIA_RESET);
udelay(1000);
dc_set_bits(sc->addr, SBE_2T3E3_21143_REG_SIA_CONNECTIVITY,
SBE_2T3E3_21143_VAL_SIA_RESET);
#endif
/* select loopback mode */
val = dc_read(sc->addr, SBE_2T3E3_21143_REG_OPERATION_MODE) &
~SBE_2T3E3_21143_VAL_OPERATING_MODE;
val |= mode;
dc_write(sc->addr, SBE_2T3E3_21143_REG_OPERATION_MODE, val);
if (mode == SBE_2T3E3_21143_VAL_LOOPBACK_OFF)
dc_set_bits(sc->addr, SBE_2T3E3_21143_REG_OPERATION_MODE,
SBE_2T3E3_21143_VAL_FULL_DUPLEX_MODE);
else
dc_clear_bits(sc->addr, SBE_2T3E3_21143_REG_OPERATION_MODE,
SBE_2T3E3_21143_VAL_FULL_DUPLEX_MODE);
}
u32 t3e3_eeprom_read_word(struct channel *channel, u32 address)
{
unsigned long addr = channel->card->bootrom_addr;
u32 i, val;
unsigned long flags;
address &= 0x3f;
spin_lock_irqsave(&channel->card->bootrom_lock, flags);
/* select correct Serial Chip */
cpld_write_nolock(channel, SBE_2T3E3_CPLD_REG_SERIAL_CHIP_SELECT,
SBE_2T3E3_CPLD_VAL_EEPROM_SELECT);
/* select reading from Serial I/O Bus */
dc_write(addr, SBE_2T3E3_21143_REG_BOOT_ROM_SERIAL_ROM_AND_MII_MANAGEMENT,
SBE_2T3E3_21143_VAL_READ_OPERATION |
SBE_2T3E3_21143_VAL_SERIAL_ROM_SELECT |
SBE_2T3E3_21143_VAL_SERIAL_ROM_CHIP_SELECT); /* clock low */
/* select read operation */
serialrom_write_bit(channel, 0);
serialrom_write_bit(channel, 1);
serialrom_write_bit(channel, 1);
serialrom_write_bit(channel, 0);
for (i = 0x20; i; i >>= 1)
serialrom_write_bit(channel, address & i ? 1 : 0);
val = 0;
for (i = 0x8000; i; i >>= 1)
val |= (serialrom_read_bit(channel) ? i : 0);
/* Reset 21143's CSR9 */
dc_write(addr, SBE_2T3E3_21143_REG_BOOT_ROM_SERIAL_ROM_AND_MII_MANAGEMENT,
SBE_2T3E3_21143_VAL_READ_OPERATION |
SBE_2T3E3_21143_VAL_SERIAL_ROM_SELECT |
SBE_2T3E3_21143_VAL_SERIAL_ROM_CHIP_SELECT); /* clock low */
dc_write(addr, SBE_2T3E3_21143_REG_BOOT_ROM_SERIAL_ROM_AND_MII_MANAGEMENT, 0);
/* Unselect Serial Chip */
cpld_write_nolock(channel, SBE_2T3E3_CPLD_REG_SERIAL_CHIP_SELECT, 0);
spin_unlock_irqrestore(&channel->card->bootrom_lock, flags);
return ntohs(val);
}
void bootrom_write(struct channel *channel, u32 reg, u32 val)
{
unsigned long addr = channel->card->bootrom_addr;
/* select BootROM address */
dc_write(addr, SBE_2T3E3_21143_REG_BOOT_ROM_PROGRAMMING_ADDRESS, reg & 0x3FFFF);
/* select writting to BootROM */
dc_write(addr, SBE_2T3E3_21143_REG_BOOT_ROM_SERIAL_ROM_AND_MII_MANAGEMENT,
SBE_2T3E3_21143_VAL_WRITE_OPERATION |
SBE_2T3E3_21143_VAL_BOOT_ROM_SELECT |
(val & 0xff));
udelay(2); /* 20 PCI cycles */
/* reset CSR9 */
dc_write(addr, SBE_2T3E3_21143_REG_BOOT_ROM_SERIAL_ROM_AND_MII_MANAGEMENT, 0);
}
static u32 serialrom_read_bit(struct channel *channel)
{
unsigned long addr = channel->card->bootrom_addr;
u32 bit;
dc_write(addr, SBE_2T3E3_21143_REG_BOOT_ROM_SERIAL_ROM_AND_MII_MANAGEMENT,
SBE_2T3E3_21143_VAL_READ_OPERATION |
SBE_2T3E3_21143_VAL_SERIAL_ROM_SELECT |
SBE_2T3E3_21143_VAL_SERIAL_ROM_CLOCK |
SBE_2T3E3_21143_VAL_SERIAL_ROM_CHIP_SELECT); /* clock high */
bit = (dc_read(addr, SBE_2T3E3_21143_REG_BOOT_ROM_SERIAL_ROM_AND_MII_MANAGEMENT) &
SBE_2T3E3_21143_VAL_SERIAL_ROM_DATA_OUT) > 0 ? 1 : 0;
dc_write(addr, SBE_2T3E3_21143_REG_BOOT_ROM_SERIAL_ROM_AND_MII_MANAGEMENT,
SBE_2T3E3_21143_VAL_READ_OPERATION |
SBE_2T3E3_21143_VAL_SERIAL_ROM_SELECT |
SBE_2T3E3_21143_VAL_SERIAL_ROM_CHIP_SELECT); /* clock low */
return bit;
}
void MakeItRobotics::turn_front_right(int speed)
{
int duty = 0;
int half = 0;
if(speed == 0)
{
duty = 0;
half = 0;
}
else if(speed >= 255)
{
duty = 1;
half = 128;
}
else
{
duty = 257 - speed;
half = 257 - speed / 2;
} dc_write(DC_CMD_DIRA, FW);
dc_write(DC_CMD_DIRB, FW);
dc_write(DC_CMD_PWMA, duty);
dc_write(DC_CMD_PWMB, half);
}
u32 bootrom_read(struct channel *channel, u32 reg)
{
unsigned long addr = channel->card->bootrom_addr;
u32 result;
/* select BootROM address */
dc_write(addr, SBE_2T3E3_21143_REG_BOOT_ROM_PROGRAMMING_ADDRESS, reg & 0x3FFFF);
/* select reading from BootROM */
dc_write(addr, SBE_2T3E3_21143_REG_BOOT_ROM_SERIAL_ROM_AND_MII_MANAGEMENT,
SBE_2T3E3_21143_VAL_READ_OPERATION |
SBE_2T3E3_21143_VAL_BOOT_ROM_SELECT);
udelay(2); /* 20 PCI cycles */
/* read from BootROM */
result = dc_read(addr, SBE_2T3E3_21143_REG_BOOT_ROM_SERIAL_ROM_AND_MII_MANAGEMENT) & 0xff;
/* reset CSR9 */
dc_write(addr, SBE_2T3E3_21143_REG_BOOT_ROM_SERIAL_ROM_AND_MII_MANAGEMENT, 0);
return result;
}
void MakeItRobotics::line_following_turn_right(int speed)
{
int duty = 0;
int half = 0;
if(speed == 0)
{
duty = 0;
half = 0;
}
else if(speed >= 255)
{
duty = 1;
half = 128;
}
else
{
duty = 257 - speed;
half = 257 - speed*3/4;
}
dc_write(DC_CMD_DIRA, FW);
dc_write(DC_CMD_DIRB, BW);
dc_write(DC_CMD_PWMA, duty);
dc_write(DC_CMD_PWMB, half);
}
void dc_start_intr(struct channel *sc)
{
if (sc->p.loopback == SBE_2T3E3_LOOPBACK_NONE && sc->s.OOF)
return;
if (sc->p.receiver_on || sc->p.transmitter_on) {
if (!sc->ether.interrupt_enable_mask)
dc_write(sc->addr, SBE_2T3E3_21143_REG_STATUS, 0xFFFFFFFF);
sc->ether.interrupt_enable_mask =
SBE_2T3E3_21143_VAL_NORMAL_INTERRUPT_SUMMARY_ENABLE |
SBE_2T3E3_21143_VAL_ABNORMAL_INTERRUPT_SUMMARY_ENABLE |
SBE_2T3E3_21143_VAL_RECEIVE_STOPPED_ENABLE |
SBE_2T3E3_21143_VAL_RECEIVE_BUFFER_UNAVAILABLE_ENABLE |
SBE_2T3E3_21143_VAL_RECEIVE_INTERRUPT_ENABLE |
SBE_2T3E3_21143_VAL_TRANSMIT_UNDERFLOW_INTERRUPT_ENABLE |
SBE_2T3E3_21143_VAL_TRANSMIT_BUFFER_UNAVAILABLE_ENABLE |
SBE_2T3E3_21143_VAL_TRANSMIT_STOPPED_ENABLE |
SBE_2T3E3_21143_VAL_TRANSMIT_INTERRUPT_ENABLE;
dc_write(sc->addr, SBE_2T3E3_21143_REG_INTERRUPT_ENABLE,
sc->ether.interrupt_enable_mask);
}
}
void dc_receiver_onoff(struct channel *sc, u32 mode)
{
u32 i, state = 0;
if (sc->p.receiver_on == mode)
return;
switch (mode) {
case SBE_2T3E3_OFF:
if (dc_read(sc->addr, SBE_2T3E3_21143_REG_OPERATION_MODE) &
SBE_2T3E3_21143_VAL_RECEIVE_START) {
dc_clear_bits(sc->addr, SBE_2T3E3_21143_REG_OPERATION_MODE,
SBE_2T3E3_21143_VAL_RECEIVE_START);
for (i = 0; i < 16; i++) {
state = dc_read(sc->addr, SBE_2T3E3_21143_REG_STATUS) &
SBE_2T3E3_21143_VAL_RECEIVE_PROCESS_STATE;
if (state == SBE_2T3E3_21143_VAL_RX_STOPPED)
break;
udelay(5);
}
if (state != SBE_2T3E3_21143_VAL_RX_STOPPED)
dev_warn(&sc->pdev->dev, "SBE 2T3E3: Rx failed to stop\n");
else
dev_info(&sc->pdev->dev, "SBE 2T3E3: Rx off\n");
}
break;
case SBE_2T3E3_ON:
dc_set_bits(sc->addr, SBE_2T3E3_21143_REG_OPERATION_MODE,
SBE_2T3E3_21143_VAL_RECEIVE_START);
udelay(100);
dc_write(sc->addr, SBE_2T3E3_21143_REG_RECEIVE_POLL_DEMAND, 0xFFFFFFFF);
break;
default:
return;
}
sc->p.receiver_on = mode;
}
void dc_reset(struct channel *sc)
{
/* turn off ethernet interrupts */
dc_write(sc->addr, SBE_2T3E3_21143_REG_INTERRUPT_ENABLE, 0);
dc_write(sc->addr, SBE_2T3E3_21143_REG_STATUS, 0xFFFFFFFF);
/* software reset */
dc_set_bits(sc->addr, SBE_2T3E3_21143_REG_BUS_MODE,
SBE_2T3E3_21143_VAL_SOFTWARE_RESET);
udelay(4); /* 50 PCI cycles < 2us */
/* clear hardware configuration */
dc_write(sc->addr, SBE_2T3E3_21143_REG_BUS_MODE, 0);
/* clear software configuration */
dc_write(sc->addr, SBE_2T3E3_21143_REG_OPERATION_MODE, 0);
/* turn off SIA reset */
dc_set_bits(sc->addr, SBE_2T3E3_21143_REG_SIA_CONNECTIVITY,
SBE_2T3E3_21143_VAL_SIA_RESET);
dc_write(sc->addr, SBE_2T3E3_21143_REG_SIA_TRANSMIT_AND_RECEIVE, 0);
dc_write(sc->addr, SBE_2T3E3_21143_REG_SIA_AND_GENERAL_PURPOSE_PORT, 0);
}
int copyfile(int src, int dest, size_t bufsize, off64_t *size, off64_t total_size)
{
ssize_t n, m ;
char * cpbuf;
size_t count;
off64_t total_bytes = 0;
size_t off;
if ( ( cpbuf = malloc(bufsize) ) == NULL ) {
perror("malloc");
return -1;
}
if( is_feedback_enabled) {
hash_printing_accept_byte_count(progress_set, 0, total_size);
}
do{
off = 0;
do{
n = dc_read(src, cpbuf + off, bufsize - off);
if( n <=0 ) break;
off += n;
} while (off != bufsize );
/* do not continue if read fails*/
if (n < 0) {
/* Read failed. */
free(cpbuf);
return -1;
}
if (off > 0) {
count = 0;
while ((count != off) && ((m = dc_write(dest, cpbuf+count, off-count)) > 0)) {
total_bytes += (off64_t)m;
count += m;
if( is_feedback_enabled) {
hash_printing_accept_byte_count(progress_set, total_bytes, total_size);
}
}
if (m < 0) {
/* Write failed. */
free(cpbuf);
return -1;
}
}
} while (n != 0);
if(size != NULL) {
*size = total_bytes;
}
if( is_feedback_enabled) {
hash_printing_accept_byte_count( progress_finished, 0, 0);
}
free(cpbuf);
return 0;
}
void MakeItRobotics::walking_robot_setup(void)
{
dc_write(DC_CMD_IR_TX1, SW_ON);
dc_write(DC_CMD_IR_TX2, SW_ON);
}
u32 dc_init_descriptor_list(struct channel *sc)
{
u32 i, j;
struct sk_buff *m;
if (sc->ether.rx_ring == NULL)
sc->ether.rx_ring = kzalloc(SBE_2T3E3_RX_DESC_RING_SIZE *
sizeof(t3e3_rx_desc_t), GFP_KERNEL);
if (sc->ether.rx_ring == NULL) {
dev_err(&sc->pdev->dev, "SBE 2T3E3: no buffer space for RX ring\n");
return ENOMEM;
}
if (sc->ether.tx_ring == NULL)
sc->ether.tx_ring = kzalloc(SBE_2T3E3_TX_DESC_RING_SIZE *
sizeof(t3e3_tx_desc_t), GFP_KERNEL);
if (sc->ether.tx_ring == NULL) {
kfree(sc->ether.rx_ring);
sc->ether.rx_ring = NULL;
dev_err(&sc->pdev->dev, "SBE 2T3E3: no buffer space for RX ring\n");
return ENOMEM;
}
/*
* Receive ring
*/
for (i = 0; i < SBE_2T3E3_RX_DESC_RING_SIZE; i++) {
sc->ether.rx_ring[i].rdes0 = SBE_2T3E3_RX_DESC_21143_OWN;
sc->ether.rx_ring[i].rdes1 =
SBE_2T3E3_RX_DESC_SECOND_ADDRESS_CHAINED | SBE_2T3E3_MTU;
if (sc->ether.rx_data[i] == NULL) {
if (!(m = dev_alloc_skb(MCLBYTES))) {
for (j = 0; j < i; j++) {
dev_kfree_skb_any(sc->ether.rx_data[j]);
sc->ether.rx_data[j] = NULL;
}
kfree(sc->ether.rx_ring);
sc->ether.rx_ring = NULL;
kfree(sc->ether.tx_ring);
sc->ether.tx_ring = NULL;
dev_err(&sc->pdev->dev, "SBE 2T3E3: token_alloc err:"
" no buffer space for RX ring\n");
return ENOBUFS;
}
sc->ether.rx_data[i] = m;
}
sc->ether.rx_ring[i].rdes2 = virt_to_phys(sc->ether.rx_data[i]->data);
sc->ether.rx_ring[i].rdes3 = virt_to_phys(
&sc->ether.rx_ring[(i + 1) % SBE_2T3E3_RX_DESC_RING_SIZE]);
}
sc->ether.rx_ring[SBE_2T3E3_RX_DESC_RING_SIZE - 1].rdes1 |=
SBE_2T3E3_RX_DESC_END_OF_RING;
sc->ether.rx_ring_current_read = 0;
dc_write(sc->addr, SBE_2T3E3_21143_REG_RECEIVE_LIST_BASE_ADDRESS,
virt_to_phys(&sc->ether.rx_ring[0]));
/*
* Transmit ring
*/
for (i = 0; i < SBE_2T3E3_TX_DESC_RING_SIZE; i++) {
sc->ether.tx_ring[i].tdes0 = 0;
sc->ether.tx_ring[i].tdes1 = SBE_2T3E3_TX_DESC_SECOND_ADDRESS_CHAINED |
SBE_2T3E3_TX_DESC_DISABLE_PADDING;
sc->ether.tx_ring[i].tdes2 = 0;
sc->ether.tx_data[i] = NULL;
sc->ether.tx_ring[i].tdes3 = virt_to_phys(
&sc->ether.tx_ring[(i + 1) % SBE_2T3E3_TX_DESC_RING_SIZE]);
}
sc->ether.tx_ring[SBE_2T3E3_TX_DESC_RING_SIZE - 1].tdes1 |=
SBE_2T3E3_TX_DESC_END_OF_RING;
dc_write(sc->addr, SBE_2T3E3_21143_REG_TRANSMIT_LIST_BASE_ADDRESS,
virt_to_phys(&sc->ether.tx_ring[0]));
sc->ether.tx_ring_current_read = 0;
sc->ether.tx_ring_current_write = 0;
sc->ether.tx_free_cnt = SBE_2T3E3_TX_DESC_RING_SIZE;
spin_lock_init(&sc->ether.tx_lock);
return 0;
}
void MakeItRobotics::sensor_kit_optical_setup(void)
{
dc_write(DC_CMD_IR_TX3, SW_ON);
}
void dc_init(struct channel *sc)
{
u32 val;
dc_stop(sc);
/*dc_reset(sc);*/ /* do not want to reset here */
/*
* BUS_MODE (CSR0)
*/
val = SBE_2T3E3_21143_VAL_READ_LINE_ENABLE |
SBE_2T3E3_21143_VAL_READ_MULTIPLE_ENABLE |
SBE_2T3E3_21143_VAL_TRANSMIT_AUTOMATIC_POLLING_200us |
SBE_2T3E3_21143_VAL_BUS_ARBITRATION_RR;
if (sc->h.command & 16)
val |= SBE_2T3E3_21143_VAL_WRITE_AND_INVALIDATE_ENABLE;
switch (sc->h.cache_size) {
case 32:
val |= SBE_2T3E3_21143_VAL_CACHE_ALIGNMENT_32;
break;
case 16:
val |= SBE_2T3E3_21143_VAL_CACHE_ALIGNMENT_16;
break;
case 8:
val |= SBE_2T3E3_21143_VAL_CACHE_ALIGNMENT_8;
break;
default:
break;
}
dc_write(sc->addr, SBE_2T3E3_21143_REG_BUS_MODE, val);
/* OPERATION_MODE (CSR6) */
val = SBE_2T3E3_21143_VAL_RECEIVE_ALL |
SBE_2T3E3_21143_VAL_MUST_BE_ONE |
SBE_2T3E3_21143_VAL_THRESHOLD_CONTROL_BITS_1 |
SBE_2T3E3_21143_VAL_LOOPBACK_OFF |
SBE_2T3E3_21143_VAL_PASS_ALL_MULTICAST |
SBE_2T3E3_21143_VAL_PROMISCUOUS_MODE |
SBE_2T3E3_21143_VAL_PASS_BAD_FRAMES;
dc_write(sc->addr, SBE_2T3E3_21143_REG_OPERATION_MODE, val);
if (sc->p.loopback == SBE_2T3E3_LOOPBACK_ETHERNET)
sc->p.loopback = SBE_2T3E3_LOOPBACK_NONE;
/*
* GENERAL_PURPOSE_TIMER_AND_INTERRUPT_MITIGATION_CONTROL (CSR11)
*/
val = SBE_2T3E3_21143_VAL_CYCLE_SIZE |
SBE_2T3E3_21143_VAL_TRANSMIT_TIMER |
SBE_2T3E3_21143_VAL_NUMBER_OF_TRANSMIT_PACKETS |
SBE_2T3E3_21143_VAL_RECEIVE_TIMER |
SBE_2T3E3_21143_VAL_NUMBER_OF_RECEIVE_PACKETS;
dc_write(sc->addr, SBE_2T3E3_21143_REG_GENERAL_PURPOSE_TIMER_AND_INTERRUPT_MITIGATION_CONTROL, val);
/* prepare descriptors and data for receive and transmit processes */
if (dc_init_descriptor_list(sc) != 0)
return;
/* clear ethernet interrupts status */
dc_write(sc->addr, SBE_2T3E3_21143_REG_STATUS, 0xFFFFFFFF);
/* SIA mode registers */
dc_set_output_port(sc);
}
void dc_stop_intr(struct channel *sc)
{
sc->ether.interrupt_enable_mask = 0;
dc_write(sc->addr, SBE_2T3E3_21143_REG_INTERRUPT_ENABLE, 0);
}
int t3e3_if_start_xmit(struct sk_buff *skb, struct net_device *dev)
{
struct channel *sc = dev_to_priv(dev);
u32 current_write, last_write;
unsigned long flags;
struct sk_buff *skb2;
if (skb == NULL) {
sc->s.out_errors++;
return 0;
}
if (sc->p.transmitter_on != SBE_2T3E3_ON) {
sc->s.out_errors++;
sc->s.out_dropped++;
dev_kfree_skb_any(skb);
return 0;
}
if (sc->s.OOF && sc->p.loopback == SBE_2T3E3_LOOPBACK_NONE) {
sc->s.out_dropped++;
dev_kfree_skb_any(skb);
return 0;
}
spin_lock_irqsave(&sc->ether.tx_lock, flags);
current_write = sc->ether.tx_ring_current_write;
for (skb2 = skb; skb2 != NULL; skb2 = NULL) {
if (skb2->len) {
if ((sc->ether.tx_ring[current_write].tdes1 &
SBE_2T3E3_TX_DESC_BUFFER_1_SIZE) > 0)
break;
current_write = (current_write + 1) % SBE_2T3E3_TX_DESC_RING_SIZE;
/*
* Leave at least 1 tx desc free so that dc_intr_tx() can
* identify empty list
*/
if (current_write == sc->ether.tx_ring_current_read)
break;
}
}
if (skb2 != NULL) {
netif_stop_queue(sc->dev);
sc->ether.tx_full = 1;
dev_dbg(&sc->pdev->dev, "SBE 2T3E3: out of descriptors\n");
spin_unlock_irqrestore(&sc->ether.tx_lock, flags);
return NETDEV_TX_BUSY;
}
current_write = last_write = sc->ether.tx_ring_current_write;
dev_dbg(&sc->pdev->dev, "sending mbuf (current_write = %d)\n",
current_write);
for (skb2 = skb; skb2 != NULL; skb2 = NULL) {
if (skb2->len) {
dev_dbg(&sc->pdev->dev,
"sending mbuf (len = %d, next = %p)\n",
skb2->len, NULL);
sc->ether.tx_free_cnt--;
sc->ether.tx_ring[current_write].tdes0 = 0;
sc->ether.tx_ring[current_write].tdes1 &=
SBE_2T3E3_TX_DESC_END_OF_RING |
SBE_2T3E3_TX_DESC_SECOND_ADDRESS_CHAINED;
/* DISABLE_PADDING sometimes gets lost somehow, hands off... */
sc->ether.tx_ring[current_write].tdes1 |=
SBE_2T3E3_TX_DESC_DISABLE_PADDING | skb2->len;
if (current_write == sc->ether.tx_ring_current_write) {
sc->ether.tx_ring[current_write].tdes1 |=
SBE_2T3E3_TX_DESC_FIRST_SEGMENT;
} else {
sc->ether.tx_ring[current_write].tdes0 =
SBE_2T3E3_TX_DESC_21143_OWN;
}
sc->ether.tx_ring[current_write].tdes2 = virt_to_phys(skb2->data);
sc->ether.tx_data[current_write] = NULL;
last_write = current_write;
current_write = (current_write + 1) % SBE_2T3E3_TX_DESC_RING_SIZE;
}
}
sc->ether.tx_data[last_write] = skb;
sc->ether.tx_ring[last_write].tdes1 |=
SBE_2T3E3_TX_DESC_LAST_SEGMENT |
SBE_2T3E3_TX_DESC_INTERRUPT_ON_COMPLETION;
sc->ether.tx_ring[sc->ether.tx_ring_current_write].tdes0 |=
SBE_2T3E3_TX_DESC_21143_OWN;
sc->ether.tx_ring_current_write = current_write;
dev_dbg(&sc->pdev->dev, "txput: tdes0 = %08X tdes1 = %08X\n",
sc->ether.tx_ring[last_write].tdes0,
sc->ether.tx_ring[last_write].tdes1);
dc_write(sc->addr, SBE_2T3E3_21143_REG_TRANSMIT_POLL_DEMAND,
0xffffffff);
spin_unlock_irqrestore(&sc->ether.tx_lock, flags);
return 0;
}
void MakeItRobotics::trigger_optical3(void)
{
dc_write(DC_CMD_IR_RX3, 0x00);
}
u32 exar7300_read(struct channel *channel, u32 reg)
{
unsigned long addr = channel->card->bootrom_addr, flags;
u32 i, val;
#if 0
switch (reg) {
case SBE_2T3E3_LIU_REG_REG1:
case SBE_2T3E3_LIU_REG_REG2:
case SBE_2T3E3_LIU_REG_REG3:
case SBE_2T3E3_LIU_REG_REG4:
return channel->liu_regs[reg];
break;
default:
}
#endif
/* select correct Serial Chip */
spin_lock_irqsave(&channel->card->bootrom_lock, flags);
cpld_write_nolock(channel, SBE_2T3E3_CPLD_REG_SERIAL_CHIP_SELECT,
cpld_val_map[SBE_2T3E3_CPLD_VAL_LIU_SELECT][channel->h.slot]);
/* select reading from Serial I/O Bus */
dc_write(addr, SBE_2T3E3_21143_REG_BOOT_ROM_SERIAL_ROM_AND_MII_MANAGEMENT,
SBE_2T3E3_21143_VAL_READ_OPERATION |
SBE_2T3E3_21143_VAL_SERIAL_ROM_SELECT |
SBE_2T3E3_21143_VAL_SERIAL_ROM_CHIP_SELECT); /* clock low */
/* select read operation */
serialrom_write_bit(channel, 1);
/* Exar7300 register address is 4 bit long */
reg = t3e3_liu_reg_map[reg];
for (i = 0; i < 4; i++, reg >>= 1) /* 4 bits of SerialROM address */
serialrom_write_bit(channel, reg & 1);
for (i = 0; i < 3; i++) /* remaining 3 bits of SerialROM address */
serialrom_write_bit(channel, 0);
val = 0; /* Exar7300 register value is 5 bit long */
for (i = 0; i < 8; i++) /* 8 bits of SerialROM value */
val += (serialrom_read_bit(channel) << i);
/* Reset 21143's CSR9 */
dc_write(addr, SBE_2T3E3_21143_REG_BOOT_ROM_SERIAL_ROM_AND_MII_MANAGEMENT,
SBE_2T3E3_21143_VAL_READ_OPERATION |
SBE_2T3E3_21143_VAL_SERIAL_ROM_SELECT |
SBE_2T3E3_21143_VAL_SERIAL_ROM_CHIP_SELECT); /* clock low */
dc_write(addr, SBE_2T3E3_21143_REG_BOOT_ROM_SERIAL_ROM_AND_MII_MANAGEMENT, 0);
/* Unselect Serial Chip */
cpld_write_nolock(channel, SBE_2T3E3_CPLD_REG_SERIAL_CHIP_SELECT, 0);
spin_unlock_irqrestore(&channel->card->bootrom_lock, flags);
return val;
}
void exar7300_write(struct channel *channel, u32 reg, u32 val)
{
unsigned long addr = channel->card->bootrom_addr, flags;
u32 i;
channel->liu_regs[reg] = val;
/* select correct Serial Chip */
spin_lock_irqsave(&channel->card->bootrom_lock, flags);
cpld_write_nolock(channel, SBE_2T3E3_CPLD_REG_SERIAL_CHIP_SELECT,
cpld_val_map[SBE_2T3E3_CPLD_VAL_LIU_SELECT][channel->h.slot]);
/* select writting to Serial I/O Bus */
dc_write(addr, SBE_2T3E3_21143_REG_BOOT_ROM_SERIAL_ROM_AND_MII_MANAGEMENT,
SBE_2T3E3_21143_VAL_WRITE_OPERATION |
SBE_2T3E3_21143_VAL_SERIAL_ROM_SELECT |
SBE_2T3E3_21143_VAL_SERIAL_ROM_CHIP_SELECT); /* clock low */
/* select write operation */
serialrom_write_bit(channel, 0);
/* Exar7300 register address is 4 bit long */
reg = t3e3_liu_reg_map[reg];
for (i = 0; i < 4; i++) { /* 4 bits */
serialrom_write_bit(channel, reg & 1);
reg >>= 1;
}
for (i = 0; i < 3; i++) /* remaining 3 bits of SerialROM address */
serialrom_write_bit(channel, 0);
/* Exar7300 register value is 5 bit long */
for (i = 0; i < 5; i++) {
serialrom_write_bit(channel, val & 1);
val >>= 1;
}
for (i = 0; i < 3; i++) /* remaining 3 bits of SerialROM value */
serialrom_write_bit(channel, 0);
/* Reset 21143_CSR9 */
dc_write(addr, SBE_2T3E3_21143_REG_BOOT_ROM_SERIAL_ROM_AND_MII_MANAGEMENT,
SBE_2T3E3_21143_VAL_WRITE_OPERATION |
SBE_2T3E3_21143_VAL_SERIAL_ROM_SELECT |
SBE_2T3E3_21143_VAL_SERIAL_ROM_CHIP_SELECT); /* clock low */
dc_write(addr, SBE_2T3E3_21143_REG_BOOT_ROM_SERIAL_ROM_AND_MII_MANAGEMENT, 0);
/* Unselect Serial Chip */
cpld_write_nolock(channel, SBE_2T3E3_CPLD_REG_SERIAL_CHIP_SELECT, 0);
spin_unlock_irqrestore(&channel->card->bootrom_lock, flags);
}
