int board_early_init_f(void) { #ifdef CONFIG_DEBUG_UART debug_uart_init(); #endif return 0; }
void early_system_init(void) { /* * The ROM will only have set up sufficient pinmux to allow for the * first 4KiB NOR to be read, we must finish doing what we know of * the NOR mux in this space in order to continue. */ #ifdef CONFIG_NOR_BOOT enable_norboot_pin_mux(); #endif watchdog_disable(); set_uart_mux_conf(); setup_early_clocks(); uart_soft_reset(); #ifdef CONFIG_SPL_BUILD /* * Save the boot parameters passed from romcode. * We cannot delay the saving further than this, * to prevent overwrites. */ save_omap_boot_params(); #endif #ifdef CONFIG_DEBUG_UART_OMAP debug_uart_init(); #endif #ifdef CONFIG_TI_I2C_BOARD_DETECT do_board_detect(); #endif #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC) /* Enable RTC32K clock */ rtc32k_enable(); #endif }
void platform_poweron() { ot_u32 prescaler = 32; /// Hardware turn-on stuff SystemInit(); // comes from STLib, does lots of startup platform_init_busclk(); // extra bus clock setup not in SystemInit() platform_init_periphclk(); // Peripherals OpenTag cares about platform_init_interruptor(); // Interrupts OpenTag cares about systim_init((void*)&prescaler); // Initialize GPTIM (to 1024 Hz) platform_init_gpio(); // Set up connections on the board platform_init_spi(); // initialize command interface to radio #if ( defined(RADIO_DEBUG) || (OT_FEATURE(MPIPE) == ENABLED) ) platform_uart_init(); #endif /* RADIO_DEBUG */ #if defined(RADIO_DEBUG) debug_uart_init(); #endif /* RADIO_DEBUG */ rng_seed(); /// Restore vworm (following save on shutdown) vworm_init(); # if (OT_FEATURE(MPIPE) == ENABLED) /// Mpipe (message pipe) typically used for serial-line comm. mpipe_init(NULL); # endif }
void board_init_f(ulong dummy) { struct udevice *pinctrl; struct udevice *dev; struct rk3399_pmusgrf_regs *sgrf; struct rk3399_grf_regs *grf; int ret; #define EARLY_UART #ifdef EARLY_UART /* * Debug UART can be used from here if required: * * debug_uart_init(); * printch('a'); * printhex8(0x1234); * printascii("string"); */ debug_uart_init(); printascii("U-Boot SPL board init"); #endif ret = spl_early_init(); if (ret) { debug("spl_early_init() failed: %d\n", ret); hang(); } /* * Disable DDR and SRAM security regions. * * As we are entered from the BootROM, the region from * 0x0 through 0xfffff (i.e. the first MB of memory) will * be protected. This will cause issues with the DW_MMC * driver, which tries to DMA from/to the stack (likely) * located in this range. */ sgrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUSGRF); rk_clrsetreg(&sgrf->ddr_rgn_con[16], 0x1ff, 0); rk_clrreg(&sgrf->slv_secure_con4, 0x2000); /* eMMC clock generator: disable the clock multipilier */ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); rk_clrreg(&grf->emmccore_con[11], 0x0ff); secure_timer_init(); ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); if (ret) { debug("Pinctrl init failed: %d\n", ret); return; } ret = uclass_get_device(UCLASS_RAM, 0, &dev); if (ret) { debug("DRAM init failed: %d\n", ret); return; } }
int board_early_init_f(void) { #ifdef CONFIG_DEBUG_UART debug_uart_init(); #endif ddr_init(); ath79_eth_reset(); return 0; }
void debug_init(void) { debug_uart_init(); debug_init_done = 1; debug_put_newline(); debug("### OpenSky - "); debug(DEFINE_TO_STR(BUILD_TARGET)); debug(" - (c) by github.com/fishpepper ###\n"); debug_flush(); debug("uart: init done\n"); }
void board_init_f(ulong dummy) { ps7_init(); arch_cpu_init(); #ifdef CONFIG_DEBUG_UART /* Uart debug for sure */ debug_uart_init(); puts("Debug uart enabled\n"); /* or printch() */ #endif }
void board_init_f(ulong dummy) { /* Example code showing how to enable the debug UART on RK3188 */ #ifdef EARLY_UART #include <asm/arch/grf_rk3188.h> /* Enable early UART on the RK3188 */ #define GRF_BASE 0x20008000 struct rk3188_grf * const grf = (void *)GRF_BASE; rk_clrsetreg(&grf->gpio1b_iomux, GPIO1B1_MASK << GPIO1B1_SHIFT | GPIO1B0_MASK << GPIO1B0_SHIFT, GPIO1B1_UART2_SOUT << GPIO1B1_SHIFT | GPIO1B0_UART2_SIN << GPIO1B0_SHIFT); /* * Debug UART can be used from here if required: * * debug_uart_init(); * printch('a'); * printhex8(0x1234); * printascii("string"); */ debug_uart_init(); printch('t'); printch('p'); printch('l'); printch('-'); printch(rk3188_num_entries + 1 + '0'); printch('\n'); #endif rk3188_num_entries++; if (rk3188_num_entries == 1) { /* * The original loader did some very basic integrity * checking at this point, but the remaining few bytes * could be used for any improvement making sense * really early on. */ back_to_bootrom(); } else { /* * TPL part of the loader should now wait for us * at offset 0xC00 in the sram. Should never return * from there. */ jump_to_spl(); } }
void spl_board_init(void) { const struct uniphier_board_data *param; #ifdef CONFIG_DEBUG_UART debug_uart_init(); #endif param = uniphier_get_board_param(); if (!param) hang(); switch (uniphier_get_soc_type()) { #if defined(CONFIG_ARCH_UNIPHIER_SLD3) case SOC_UNIPHIER_SLD3: uniphier_sld3_init(param); break; #endif #if defined(CONFIG_ARCH_UNIPHIER_LD4) case SOC_UNIPHIER_LD4: uniphier_ld4_init(param); break; #endif #if defined(CONFIG_ARCH_UNIPHIER_PRO4) case SOC_UNIPHIER_PRO4: uniphier_pro4_init(param); break; #endif #if defined(CONFIG_ARCH_UNIPHIER_SLD8) case SOC_UNIPHIER_SLD8: uniphier_sld8_init(param); break; #endif #if defined(CONFIG_ARCH_UNIPHIER_PRO5) case SOC_UNIPHIER_PRO5: uniphier_pro5_init(param); break; #endif #if defined(CONFIG_ARCH_UNIPHIER_PXS2) || defined(CONFIG_ARCH_UNIPHIER_LD6B) case SOC_UNIPHIER_PXS2: case SOC_UNIPHIER_LD6B: uniphier_pxs2_init(param); break; #endif default: break; } }
void board_init_f(ulong dummy) { struct udevice *dev; int ret; /* Example code showing how to enable the debug UART on RK3288 */ /* Enable early UART on the RK3288 */ struct rk3288_grf * const grf = (void *)GRF_BASE; rk_clrsetreg(&grf->gpio7ch_iomux, GPIO7C7_MASK << GPIO7C7_SHIFT | GPIO7C6_MASK << GPIO7C6_SHIFT, GPIO7C7_UART2DBG_SOUT << GPIO7C7_SHIFT | GPIO7C6_UART2DBG_SIN << GPIO7C6_SHIFT); /* * Debug UART can be used from here if required: * * debug_uart_init(); * printch('a'); * printhex8(0x1234); * printascii("string"); */ debug_uart_init(); ret = spl_early_init(); if (ret) { debug("spl_early_init() failed: %d\n", ret); hang(); } rockchip_timer_init(); configure_l2ctlr(); ret = rockchip_get_clk(&dev); if (ret) { debug("CLK init failed: %d\n", ret); return; } ret = uclass_get_device(UCLASS_RAM, 0, &dev); if (ret) { debug("DRAM init failed: %d\n", ret); return; } }
void board_init_f(ulong dummy) { psu_init(); board_early_init_r(); #ifdef CONFIG_DEBUG_UART /* Uart debug for sure */ debug_uart_init(); puts("Debug uart enabled\n"); /* or printch() */ #endif /* Delay is required for clocks to be propagated */ udelay(1000000); /* Clear the BSS */ memset(__bss_start, 0, __bss_end - __bss_start); /* No need to call timer init - it is empty for ZynqMP */ board_init_r(NULL, 0); }
void board_init_f(ulong dummy) { #ifdef EARLY_DEBUG /* * NOTE: sd card and debug uart use same iomux in rk3036, * so if you enable uart, * you can not boot from sdcard */ rk_clrsetreg(&grf->gpio1c_iomux, GPIO1C3_MASK << GPIO1C3_SHIFT | GPIO1C2_MASK << GPIO1C2_SHIFT, GPIO1C3_UART2_SOUT << GPIO1C3_SHIFT | GPIO1C2_UART2_SIN << GPIO1C2_SHIFT); debug_uart_init(); #endif rockchip_timer_init(); sdram_init(); /* return to maskrom */ back_to_bootrom(); }
int main(void) { prvSetupHardware(); debug_uart_init(); LOG_INFO("Initializing hardware"); hardware_init(); /* LED1 toggle thread */ LOG_INFO("Starting tasks"); xTaskCreate(vBootSystem, NULL, 256, NULL, (tskIDLE_PRIORITY + 2), &boot_handle); LOG_INFO("Tasks created; Starting scheduler"); /* Start the scheduler */ vTaskStartScheduler(); exit_error(ERROR_CODE_MAIN_SCHEDULER_FALL_THRU); /* Should never arrive here */ return 1; }
void board_init_f(ulong boot_flags) { #ifdef CONFIG_SYS_GENERIC_GLOBAL_DATA /* * For some archtectures, global data is initialized and used before * calling this function. The data should be preserved. For others, * CONFIG_SYS_GENERIC_GLOBAL_DATA should be defined and use the stack * here to host global data until relocation. */ gd_t data; gd = &data; /* * Clear global data before it is accessed at debug print * in initcall_run_list. Otherwise the debug print probably * get the wrong vaule of gd->have_console. */ zero_global_data(); #endif gd->flags = boot_flags; gd->have_console = 0; #ifdef CONFIG_DEBUG_UART //exynos_pinmux_config(PERIPH_ID_UART2, PINMUX_FLAG_NONE); debug_uart_init(); #endif if (initcall_run_list(init_sequence_f)) hang(); #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \ !defined(CONFIG_EFI_APP) /* NOTREACHED - jump_to_copy() does not return */ hang(); #endif }
void main_task(void *args) { debug_uart_init(); debug_puts("\r\nTimer Test\r\n"); timer_init(); for (;;) { timer_tick_t ticks = timer_get_ticks(); debug_printf("time: %llu usec (%.3f sec)\r\n", ticks, (double)ticks / 1000000.0); uint16_t ppm[PPM_MAX_CHANNELS]; size_t len = timer_get_ppm(ppm, PPM_MAX_CHANNELS, NULL); debug_printf("ppm: "); for (int i = 0; i < len; ++i) debug_printf("%u ", ppm[i]); debug_printf("\r\n\r\n"); vTaskDelay(1000); } }
inline void app_init() { debug_uart_init(); static char * run = "\n\rReseted\n\r"; debug_uart_write(run); tuner_init(); tuner_audio_init(); tuner_control_pwr(true); config.event_callback = usb_event; config.ct_request_callback = &app_usb_ct_handler; usb_init(&config); static Usb_audio_iface uai; audio_if = &uai; usb_audio_init(audio_if, 1, NULL); Usb_audio_add_ep(audio_if, USB_EP01, USB_EP_IN, app_usb_audio_td0_handler); tunnel_init(); static char *initd = "init done\n\r"; debug_uart_write(initd); }
int board_early_init_f(void) { void __iomem *regs; regs = map_physmem(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE, MAP_NOCACHE); /* Assure JTAG is not disconnected. */ writel(0x40, regs + AR934X_GPIO_REG_FUNC); /* Configure default GPIO input/output regs. */ writel(0x3031b, regs + AR71XX_GPIO_REG_OE); writel(0x0f804, regs + AR71XX_GPIO_REG_OUT); /* Configure pin multiplexing. */ writel(0x00000000, regs + AR934X_GPIO_REG_OUT_FUNC0); writel(0x0b0a0980, regs + AR934X_GPIO_REG_OUT_FUNC1); writel(0x00180000, regs + AR934X_GPIO_REG_OUT_FUNC2); writel(0x00000000, regs + AR934X_GPIO_REG_OUT_FUNC3); writel(0x0000004d, regs + AR934X_GPIO_REG_OUT_FUNC4); writel(0x00000000, regs + AR934X_GPIO_REG_OUT_FUNC5); #ifdef CONFIG_DEBUG_UART debug_uart_init(); #endif #ifndef CONFIG_SKIP_LOWLEVEL_INIT ar934x_pll_init(560, 480, 240); ar934x_ddr_init(560, 480, 240); #endif wdr4300_usb_start(); ath79_eth_reset(); return 0; }
void board_init_f(ulong dummy) { struct udevice *pinctrl; struct udevice *dev; int ret; /* Example code showing how to enable the debug UART on RK3288 */ #include <asm/arch/grf_rk3288.h> /* Enable early UART on the RK3288 */ #define GRF_BASE 0xff770000 struct rk3288_grf * const grf = (void *)GRF_BASE; rk_clrsetreg(&grf->gpio7ch_iomux, GPIO7C7_MASK << GPIO7C7_SHIFT | GPIO7C6_MASK << GPIO7C6_SHIFT, GPIO7C7_UART2DBG_SOUT << GPIO7C7_SHIFT | GPIO7C6_UART2DBG_SIN << GPIO7C6_SHIFT); /* * Debug UART can be used from here if required: * * debug_uart_init(); * printch('a'); * printhex8(0x1234); * printascii("string"); */ debug_uart_init(); debug("\nspl:debug uart enabled in %s\n", __func__); ret = spl_early_init(); if (ret) { debug("spl_early_init() failed: %d\n", ret); hang(); } rockchip_timer_init(); configure_l2ctlr(); ret = rockchip_get_clk(&dev); if (ret) { debug("CLK init failed: %d\n", ret); return; } ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); if (ret) { debug("Pinctrl init failed: %d\n", ret); return; } #if !defined(CONFIG_SPL_OF_PLATDATA) if (of_machine_is_compatible("phytec,rk3288-phycore-som")) { ret = phycore_init(); if (ret) { debug("Failed to set up phycore power settings: %d\n", ret); return; } } #endif #if !defined(CONFIG_SUPPORT_TPL) debug("\nspl:init dram\n"); ret = uclass_get_device(UCLASS_RAM, 0, &dev); if (ret) { debug("DRAM init failed: %d\n", ret); return; } #endif #if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT) back_to_bootrom(BROM_BOOT_NEXTSTAGE); #endif }
void board_init_f(ulong dummy) { const struct cm_config *cm_default_cfg = cm_get_default_config(); unsigned long sdram_size; unsigned long reg; int ret; /* * First C code to run. Clear fake OCRAM ECC first as SBE * and DBE might triggered during power on */ reg = readl(&sysmgr_regs->eccgrp_ocram); if (reg & SYSMGR_ECC_OCRAM_SERR) writel(SYSMGR_ECC_OCRAM_SERR | SYSMGR_ECC_OCRAM_EN, &sysmgr_regs->eccgrp_ocram); if (reg & SYSMGR_ECC_OCRAM_DERR) writel(SYSMGR_ECC_OCRAM_DERR | SYSMGR_ECC_OCRAM_EN, &sysmgr_regs->eccgrp_ocram); memset(__bss_start, 0, __bss_end - __bss_start); socfpga_sdram_remap_zero(); debug("Freezing all I/O banks\n"); /* freeze all IO banks */ sys_mgr_frzctrl_freeze_req(); /* Put everything into reset but L4WD0. */ socfpga_per_reset_all(); if (!socfpga_is_booting_from_fpga()) { /* Put FPGA bridges into reset too. */ socfpga_bridges_reset(1); } socfpga_per_reset(SOCFPGA_RESET(SDR), 0); socfpga_per_reset(SOCFPGA_RESET(UART0), 0); socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0); timer_init(); debug("Reconfigure Clock Manager\n"); /* reconfigure the PLLs */ if (cm_basic_init(cm_default_cfg)) hang(); /* Enable bootrom to configure IOs. */ sysmgr_config_warmrstcfgio(1); /* configure the IOCSR / IO buffer settings */ if (scan_mgr_configure_iocsr()) hang(); sysmgr_config_warmrstcfgio(0); /* configure the pin muxing through system manager */ sysmgr_config_warmrstcfgio(1); sysmgr_pinmux_init(); sysmgr_config_warmrstcfgio(0); /* De-assert reset for peripherals and bridges based on handoff */ reset_deassert_peripherals_handoff(); socfpga_bridges_reset(0); debug("Unfreezing/Thaw all I/O banks\n"); /* unfreeze / thaw all IO banks */ sys_mgr_frzctrl_thaw_req(); #ifdef CONFIG_DEBUG_UART socfpga_per_reset(SOCFPGA_RESET(UART0), 0); debug_uart_init(); #endif ret = spl_early_init(); if (ret) { debug("spl_early_init() failed: %d\n", ret); hang(); } /* enable console uart printing */ preloader_console_init(); if (sdram_mmr_init_full(0xffffffff) != 0) { puts("SDRAM init failed.\n"); hang(); } debug("SDRAM: Calibrating PHY\n"); /* SDRAM calibration */ if (sdram_calibration_full() == 0) { puts("SDRAM calibration failed.\n"); hang(); } sdram_size = sdram_calculate_size(); debug("SDRAM: %ld MiB\n", sdram_size >> 20); /* Sanity check ensure correct SDRAM size specified */ if (get_ram_size(0, sdram_size) != sdram_size) { puts("SDRAM size check failed!\n"); hang(); } if (!socfpga_is_booting_from_fpga()) socfpga_bridges_reset(1); }
void board_init_f(ulong dummy) { struct udevice *pinctrl, *dev; struct rk3188_pmu *pmu; int ret; /* Example code showing how to enable the debug UART on RK3188 */ #ifdef EARLY_UART #include <asm/arch/grf_rk3188.h> /* Enable early UART on the RK3188 */ #define GRF_BASE 0x20008000 struct rk3188_grf * const grf = (void *)GRF_BASE; rk_clrsetreg(&grf->gpio1b_iomux, GPIO1B1_MASK << GPIO1B1_SHIFT | GPIO1B0_MASK << GPIO1B0_SHIFT, GPIO1B1_UART2_SOUT << GPIO1B1_SHIFT | GPIO1B0_UART2_SIN << GPIO1B0_SHIFT); /* * Debug UART can be used from here if required: * * debug_uart_init(); * printch('a'); * printhex8(0x1234); * printascii("string"); */ debug_uart_init(); printch('s'); printch('p'); printch('l'); printch('\n'); #endif ret = spl_early_init(); if (ret) { debug("spl_early_init() failed: %d\n", ret); hang(); } rockchip_timer_init(); ret = rockchip_get_clk(&dev); if (ret) { debug("CLK init failed: %d\n", ret); return; } /* * Recover the bootrom's stackpointer. * For whatever reason needs to run after rockchip_get_clk. */ pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU); if (IS_ERR(pmu)) error("pmu syscon returned %ld\n", PTR_ERR(pmu)); SAVE_SP_ADDR = readl(&pmu->sys_reg[2]); ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); if (ret) { debug("Pinctrl init failed: %d\n", ret); return; } ret = uclass_get_device(UCLASS_RAM, 0, &dev); if (ret) { debug("DRAM init failed: %d\n", ret); return; } setup_arm_clock(); #if defined(CONFIG_ROCKCHIP_SPL_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT) back_to_bootrom(); #endif }
void board_init_f(ulong dummy) { struct udevice *pinctrl, *dev; int ret; /* Example code showing how to enable the debug UART on RK3188 */ #ifdef EARLY_UART #include <asm/arch/grf_rk3188.h> /* Enable early UART on the RK3188 */ #define GRF_BASE 0x20008000 struct rk3188_grf * const grf = (void *)GRF_BASE; rk_clrsetreg(&grf->gpio1b_iomux, GPIO1B1_MASK << GPIO1B1_SHIFT | GPIO1B0_MASK << GPIO1B0_SHIFT, GPIO1B1_UART2_SOUT << GPIO1B1_SHIFT | GPIO1B0_UART2_SIN << GPIO1B0_SHIFT); /* * Debug UART can be used from here if required: * * debug_uart_init(); * printch('a'); * printhex8(0x1234); * printascii("string"); */ debug_uart_init(); printch('s'); printch('p'); printch('l'); printch('\n'); #endif ret = spl_early_init(); if (ret) { debug("spl_early_init() failed: %d\n", ret); hang(); } ret = rockchip_get_clk(&dev); if (ret) { debug("CLK init failed: %d\n", ret); return; } ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); if (ret) { debug("Pinctrl init failed: %d\n", ret); return; } ret = uclass_get_device(UCLASS_RAM, 0, &dev); if (ret) { debug("DRAM init failed: %d\n", ret); return; } setup_arm_clock(); #if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT) back_to_bootrom(BROM_BOOT_NEXTSTAGE); #endif }