/*
* Dump some core clockes.
*/
int do_mx7_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
u32 addr = 0;
u32 freq;
freq = decode_pll(PLL_A7_SPLL);
printf("PLL_A7_SPLL %8d MHz\n", freq / 1000000);
freq = decode_pll(PLL_A7_APLL);
printf("PLL_A7_APLL %8d MHz\n", freq / 1000000);
freq = decode_pll(PLL_USB);
printf("PLL_USB %8d MHz\n", freq / 1000000);
printf("\n");
printf("CORE %8d kHz\n", scg_clk_get_rate(SCG_CORE_CLK) / 1000);
printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
printf("UART %8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000);
printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000);
printf("AXI %8d kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000);
printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
printf("USDHC1 %8d kHz\n", mxc_get_clock(MXC_ESDHC_CLK) / 1000);
printf("USDHC2 %8d kHz\n", mxc_get_clock(MXC_ESDHC2_CLK) / 1000);
printf("I2C4 %8d kHz\n", mxc_get_clock(MXC_I2C_CLK) / 1000);
addr = (u32) clock_init;
printf("[%s] addr = 0x%08X\r\n", __func__, addr);
scg_a7_info();
return 0;
}
static u32 mxc_get_pll_pfd(enum pll_clocks pll, int pfd_num)
{
u32 div;
u64 freq;
switch (pll) {
case PLL_BUS:
if (!is_cpu_type(MXC_CPU_MX6UL)) {
if (pfd_num == 3) {
/* No PFD3 on PPL2 */
return 0;
}
}
div = __raw_readl(&imx_ccm->analog_pfd_528);
freq = (u64)decode_pll(PLL_BUS, MXC_HCLK);
break;
case PLL_USBOTG:
div = __raw_readl(&imx_ccm->analog_pfd_480);
freq = (u64)decode_pll(PLL_USBOTG, MXC_HCLK);
break;
default:
/* No PFD on other PLL */
return 0;
}
return lldiv(freq * 18, (div & ANATOP_PFD_FRAC_MASK(pfd_num)) >>
ANATOP_PFD_FRAC_SHIFT(pfd_num));
}
u32 get_periph_clk(void)
{
u32 reg, freq = 0;
u32 div;
reg = __raw_readl(&imx_ccm->cbcdr);
if (reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
div = (reg & MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK) >>
MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET;
reg = __raw_readl(&imx_ccm->cbcmr);
reg &= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK;
reg >>= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET;
switch (reg) {
case 0:
freq = decode_pll(PLL_USBOTG, MXC_HCLK);
break;
case 1:
case 2:
freq = MXC_HCLK;
break;
default:
break;
}
} else {
static u32 get_mcu_main_clk(void)
{
u32 reg, freq;
reg = __raw_readl(&imx_ccm->cacrr);
reg &= MXC_CCM_CACRR_ARM_PODF_MASK;
reg >>= MXC_CCM_CACRR_ARM_PODF_OFFSET;
freq = decode_pll(PLL_SYS, MXC_HCLK);
return freq / (reg + 1);
}