/* Return 0, 3, or 5 to indicate the previous sleep state. */ int soc_prev_sleep_state(const struct chipset_power_state *ps, int prev_sleep_state) { /* * Check for any power failure to determine if this a wake from * S5 because the PCH does not set the WAK_STS bit when waking * from a true G3 state. */ if (!(ps->pm1_sts & WAK_STS) && (ps->gen_pmcon_b & (PWR_FLR | SUS_PWR_FLR))) prev_sleep_state = ACPI_S5; /* * If waking from S3 determine if deep S3 is enabled. If not, * need to check both deep sleep well and normal suspend well. * Otherwise just check deep sleep well. */ if (prev_sleep_state == ACPI_S3) { /* PWR_FLR represents deep sleep power well loss. */ uint32_t mask = PWR_FLR; /* If deep s3 isn't enabled check the suspend well too. */ if (!deep_s3_enabled()) mask |= SUS_PWR_FLR; if (ps->gen_pmcon_b & mask) prev_sleep_state = ACPI_S5; } return prev_sleep_state; }
/* Return 0, 3, or 5 to indicate the previous sleep state. */ static uint32_t prev_sleep_state(struct chipset_power_state *ps) { /* Default to S0. */ uint32_t prev_sleep_state = SLEEP_STATE_S0; if (ps->pm1_sts & WAK_STS) { switch ((ps->pm1_cnt & SLP_TYP) >> SLP_TYP_SHIFT) { #if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) case SLP_TYP_S3: prev_sleep_state = SLEEP_STATE_S3; break; #endif case SLP_TYP_S5: prev_sleep_state = SLEEP_STATE_S5; break; } /* Clear SLP_TYP. */ outl(ps->pm1_cnt & ~(SLP_TYP), ACPI_BASE_ADDRESS + PM1_CNT); } /* * If waking from S3 determine if deep S3 is enabled. If not, * need to check both deep sleep well and normal suspend well. * Otherwise just check deep sleep well. */ if (prev_sleep_state == SLEEP_STATE_S3) { /* PWR_FLR represents deep sleep power well loss. */ uint32_t mask = PWR_FLR; /* If deep s3 isn't enabled check the suspend well too. */ if (!deep_s3_enabled()) mask |= SUS_PWR_FLR; if (ps->gen_pmcon_b & mask) prev_sleep_state = SLEEP_STATE_S5; } return prev_sleep_state; }