static void vexpress_reset_do(struct device *dev, const char *what) { int err = -ENOENT; struct regmap *reg = dev_get_drvdata(dev); if (reg) { err = regmap_write(reg, 0, 0); if (!err) mdelay(1000); } dev_emerg(dev, "Unable to %s (%d)\n", what, err); }
/* * The open implementation. */ static int kern_open(struct inode *inode, struct file *filp) { /* you can use dev_printk like you would printk only with the added device... */ dev_printk(KERN_DEBUG, my_device, "this is my debug message"); /* or better yet, use the predefined ones: */ dev_emerg(my_device, "emergency"); dev_alert(my_device, "alert"); dev_crit(my_device, "critical"); dev_err(my_device, "error"); dev_warn(my_device, "warning"); dev_notice(my_device, "notice"); dev_info(my_device, "info"); return 0; }
static void xgene_restart(enum reboot_mode mode, const char *cmd) { struct xgene_reboot_context *ctx = xgene_restart_ctx; unsigned long timeout; /* Issue the reboot */ if (ctx) writel(ctx->mask, ctx->csr); timeout = jiffies + HZ; while (time_before(jiffies, timeout)) cpu_relax(); dev_emerg(&ctx->pdev->dev, "Unable to restart system\n"); }
static void vexpress_reset_do(struct device *dev, const char *what) { int err = -ENOENT; struct vexpress_config_func *func = vexpress_config_func_get_by_dev(dev); if (func) { unsigned long timeout; err = vexpress_config_write(func, 0, 0); timeout = jiffies + HZ; while (time_before(jiffies, timeout)) cpu_relax(); } dev_emerg(dev, "Unable to %s (%d)\n", what, err); }
static int intel_815_configure(void) { u32 temp, addr; u8 temp2; struct aper_size_info_8 *current_size; /* attbase - aperture base */ /* the Intel 815 chipset spec. says that bits 29-31 in the * ATTBASE register are reserved -> try not to write them */ if (agp_bridge->gatt_bus_addr & INTEL_815_ATTBASE_MASK) { dev_emerg(&agp_bridge->dev->dev, "gatt bus addr too high"); return -EINVAL; } current_size = A_SIZE_8(agp_bridge->current_size); /* aperture size */ pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); /* address to map to */ pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); pci_read_config_dword(agp_bridge->dev, INTEL_ATTBASE, &addr); addr &= INTEL_815_ATTBASE_MASK; addr |= agp_bridge->gatt_bus_addr; pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, addr); /* agpctrl */ pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); /* apcont */ pci_read_config_byte(agp_bridge->dev, INTEL_815_APCONT, &temp2); pci_write_config_byte(agp_bridge->dev, INTEL_815_APCONT, temp2 | (1 << 1)); /* clear any possible error conditions */ /* Oddness : this chipset seems to have no ERRSTS register ! */ return 0; }
static int intel_815_configure(void) { u32 temp, addr; u8 temp2; struct aper_size_info_8 *current_size; if (agp_bridge->gatt_bus_addr & INTEL_815_ATTBASE_MASK) { dev_emerg(&agp_bridge->dev->dev, "gatt bus addr too high"); return -EINVAL; } current_size = A_SIZE_8(agp_bridge->current_size); pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); pci_read_config_dword(agp_bridge->dev, INTEL_ATTBASE, &addr); addr &= INTEL_815_ATTBASE_MASK; addr |= agp_bridge->gatt_bus_addr; pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, addr); pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); pci_read_config_byte(agp_bridge->dev, INTEL_815_APCONT, &temp2); pci_write_config_byte(agp_bridge->dev, INTEL_815_APCONT, temp2 | (1 << 1)); return 0; }