static void ctrl_init(struct device *dev) { /* * TODO: Fix some ordering issue for V-link set Rx77[6] and * PCI1_Rx4F[0] should to 1. * FIXME DO you need? */ /* * VT8237R specific configuration. Other SB are done in their own * directories. TODO: Add A version. */ device_t devsb = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237S_LPC, 0); if (devsb) { vt8237s_vlink_init(dev); } devsb = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237A_LPC, 0); if (devsb) { vt8237a_vlink_init(dev); } /* Configure PCI1 and copy mirror registers from D0F3. */ vt8237_cfg(dev); dump_south(dev); }
static void vt8237_cfg(struct device *dev) { u8 regm, regm3; device_t devfun3; devfun3 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_K8T800_DRAM, 0); if (!devfun3) devfun3 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_K8M800_DRAM, 0); if (!devfun3) devfun3 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_K8T890CE_3, 0); if (!devfun3) devfun3 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_K8M890CE_3, 0); if (!devfun3) devfun3 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_K8T890CF_3, 0); if (!devfun3) die("Unknown NB"); /* CPU to PCI Flow Control 1 & 2, just fill in recommended. */ pci_write_config8(dev, 0x70, 0xc2); pci_write_config8(dev, 0x71, 0xc8); /* PCI Control */ pci_write_config8(dev, 0x72, 0xee); pci_write_config8(dev, 0x73, 0x01); pci_write_config8(dev, 0x74, 0x3c); pci_write_config8(dev, 0x75, 0x0f); pci_write_config8(dev, 0x76, 0x50); pci_write_config8(dev, 0x77, 0x48); pci_write_config8(dev, 0x78, 0x01); /* APIC on HT */ /* Maybe Enable LDT APIC Mode bit3 set to 1 */ pci_write_config8(dev, 0x7c, 0x77); /* WARNING: Need to copy some registers from NB (D0F3) to SB (D11F7). */ regm = pci_read_config8(devfun3, 0x88); /* Shadow mem CTRL */ pci_write_config8(dev, 0x57, regm); regm = pci_read_config8(devfun3, 0x80); /* Shadow page C */ pci_write_config8(dev, 0x61, regm); regm = pci_read_config8(devfun3, 0x81); /* Shadow page D */ pci_write_config8(dev, 0x62, regm); /* Shadow page F + memhole copy */ regm = pci_read_config8(devfun3, 0x83); pci_write_config8(dev, 0x63, regm); // FIXME is this really supposed to be regm3? regm3 = pci_read_config8(devfun3, 0x82);/* Shadow page E */ pci_write_config8(dev, 0x64, regm); regm = pci_read_config8(devfun3, 0x86); /* SMM and APIC decoding */ pci_write_config8(dev, 0xe6, regm); }
static void vt8237r_cfg(struct device *dev, struct device *devsb) { u8 regm, regm3; device_t devfun3; devfun3 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_K8T890CE_3, 0); if (!devfun3) devfun3 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_K8M890CE_3, 0); pci_write_config8(dev, 0x70, 0xc2); /* PCI Control */ pci_write_config8(dev, 0x72, 0xee); pci_write_config8(dev, 0x73, 0x01); pci_write_config8(dev, 0x74, 0x24); pci_write_config8(dev, 0x75, 0x0f); pci_write_config8(dev, 0x76, 0x50); pci_write_config8(dev, 0x77, 0x08); pci_write_config8(dev, 0x78, 0x01); /* APIC on HT */ pci_write_config8(dev, 0x7c, 0x7f); pci_write_config8(dev, 0x7f, 0x02); /* WARNING: Need to copy some registers from NB (D0F3) to SB (D0F7). */ regm = pci_read_config8(devfun3, 0x88); /* Shadow mem CTRL */ pci_write_config8(dev, 0x57, regm); regm = pci_read_config8(devfun3, 0x80); /* Shadow page C */ pci_write_config8(dev, 0x61, regm); regm = pci_read_config8(devfun3, 0x81); /* Shadow page D */ pci_write_config8(dev, 0x62, regm); regm = pci_read_config8(devfun3, 0x86); /* SMM and APIC decoding */ pci_write_config8(dev, 0xe6, regm); regm3 = pci_read_config8(devfun3, 0x82);/* Shadow page E */ /* * All access bits for 0xE0000-0xEFFFF encode as just 2 bits! * So the NB reg is quite inconsistent, we expect there only 0xff or 0x00, * and write them to 0x63 7-6 but! VIA 8237A has the mirror at 0x64! */ if (regm3 == 0xff) regm3 = 0xc0; else regm3 = 0x0; /* Shadow page F + memhole copy */ regm = pci_read_config8(devfun3, 0x83); pci_write_config8(dev, 0x63, regm3 | (regm & 0x3F)); }
u32 uart_mem_init(void) { unsigned uart_baud = CONFIG_TTYS0_BAUD; u32 uart_bar = 0; unsigned div; /* find out the correct baud rate */ #if !defined(__SMM__) && CONFIG_USE_OPTION_TABLE static const unsigned baud[8] = { 115200, 57600, 38400, 19200, 9600, 4800, 2400, 1200 }; unsigned b_index = 0; #if defined(__PRE_RAM__) b_index = read_option(baud_rate, 0); b_index &= 7; uart_baud = baud[b_index]; #else if (get_option(&b_index, "baud_rate") == CB_SUCCESS) uart_baud = baud[b_index]; #endif #endif /* Now find the UART base address and calculate the divisor */ #if CONFIG_DRIVERS_OXFORD_OXPCIE #if defined(MORE_TESTING) && !defined(__SIMPLE_DEVICE__) device_t dev = dev_find_device(0x1415, 0xc158, NULL); if (!dev) dev = dev_find_device(0x1415, 0xc11b, NULL); if (dev) { struct resource *res = find_resource(dev, 0x10); if (res) { uart_bar = res->base + 0x1000; // for 1st UART // uart_bar = res->base + 0x2000; // for 2nd UART } } if (!uart_bar) #endif uart_bar = CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000; // 1st UART // uart_bar = CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x2000; // 2nd UART div = 4000000 / uart_baud; #endif if (uart_bar) uart8250_mem_init(uart_bar, div); return uart_bar; }
static void write_protect_vgabios(void) { device_t dev; printk(BIOS_DEBUG, "write_protect_vgabios\n"); dev = dev_find_device(PCI_VENDOR_ID_VIA, 0x3324, 0); if (dev) pci_write_config8(dev, 0x80, 0xff); dev = dev_find_device(PCI_VENDOR_ID_VIA, 0x7324, 0); if (dev) pci_write_config8(dev, 0x61, 0xff); }
unsigned long acpi_fill_mcfg(unsigned long current) { device_t dev; u32 pciexbar = 0; u32 pciexbar_reg; int max_buses; int pci_dev_id; for (pci_dev_id = PCI_DEVICE_ID_RG_MIN; pci_dev_id <= PCI_DEVICE_ID_RG_MAX; pci_dev_id++) { dev = dev_find_device(PCI_VENDOR_ID_INTEL, pci_dev_id, 0); if (dev) break; } if (!dev) return current; pciexbar_reg = sideband_read(B_UNIT, BECREG); /* MMCFG not supported or not enabled. */ if (!(pciexbar_reg & (1 << 0))) return current; /* 256MB ECAM range */ pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)); max_buses = 256; current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current, pciexbar, 0x0, 0x0, max_buses - 1); return current; }
static void init(struct device *dev) { unsigned int gpio_base, i; printk(BIOS_DEBUG, "LiPPERT LiteRunner-LX ENTER %s\n", __func__); /* Init CS5536 GPIOs */ gpio_base = pci_read_config32(dev_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, 0), PCI_BASE_ADDRESS_1) - 1; outl(0x00000040, gpio_base + 0x00); // GPIO6 value 1 - LAN_PD# outl(0x00000040, gpio_base + 0x04); // GPIO6 output 1 - LAN_PD# outl(0x04000000, gpio_base + 0x18); // GPIO10 pull up 0 - THRM_ALRM# outl(0x00000400, gpio_base + 0x34); // GPIO10 in aux1 1 - THRM_ALRM# outl(0x00000400, gpio_base + 0x20); // GPIO10 input 1 - THRM_ALRM# outl(0x00000800, gpio_base + 0x94); // GPIO27 out aux2 1 - 32kHz outl(0x00000800, gpio_base + 0x84); // GPIO27 output 1 - 32kHz outl(0x08000000, gpio_base + 0x98); // GPIO27 pull up 0 - 32kHz /* Init Environment Controller. */ for (i = 0; i < ARRAY_SIZE(ec_init_table); i++) { u16 val = ec_init_table[i]; outb((u8)val, 0x0295); outb(val >> 8, 0x0296); } /* bit2 = RS485_EN2, bit1 = RS485_EN1, bit0 = Live LED */ outb(SIO_GP1X_CONFIG, 0x1220); /* Simple-I/O GP17-10 */ /* bit1 = COM3_RX_EN, bit0 = COM3_TX_EN */ outb(SIO_GP2X_CONFIG, 0x1221); /* Simple-I/O GP27-20 */ printk(BIOS_DEBUG, "LiPPERT LiteRunner-LX EXIT %s\n", __func__); }
static void init(struct device *dev) { unsigned int gpio_base, i; printk(BIOS_DEBUG, "LiPPERT Hurricane-LX ENTER %s\n", __func__); /* Init CS5536 GPIOs */ gpio_base = pci_read_config32(dev_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, 0), PCI_BASE_ADDRESS_1) - 1; outl(0x00000040, gpio_base + 0x00); // GPIO6 value 1 - LAN_PD# outl(0x00000040, gpio_base + 0x08); // GPIO6 open drain 1 - LAN_PD# (jumpered GPIO per default) outl(0x00000040, gpio_base + 0x04); // GPIO6 output 1 - LAN_PD# outl(0x00000400, gpio_base + 0x34); // GPIO10 in aux1 1 - THRM_ALRM# outl(0x00000400, gpio_base + 0x20); // GPIO10 input 1 - THRM_ALRM# #if !CONFIG_BOARD_OLD_REVISION outl(0x00000800, gpio_base + 0x94); // GPIO27 out aux2 1 - 32kHz outl(0x00000800, gpio_base + 0x84); // GPIO27 output 1 - 32kHz #endif outl(0x08000000, gpio_base + 0x98); // GPIO27 pull up 0 - 32kHz (new) / PM-LED (old) /* Init Environment Controller. */ for (i = 0; i < ARRAY_SIZE(ec_init_table); i++) { u16 val = ec_init_table[i]; outb((u8)val, 0x0295); outb(val >> 8, 0x0296); } /* bit2 = RS485_EN2, bit1 = RS485_EN1 */ outb(SIO_GP1X_CONFIG, 0x1220); /* Simple-I/O GP17-10 */ printk(BIOS_DEBUG, "LiPPERT Hurricane-LX EXIT %s\n", __func__); }
void set_led(void) { // set power led to steady now that coreboot has virtually done its job device_t dev; dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, 0); pci_write_config8(dev, 0x94, 0xb0); }
u32 vt8237_ide_80pin_detect(struct device *dev) { device_t lpc_dev; u16 acpi_io_base; u32 gpio_in; u32 res; lpc_dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237A_LPC, 0); if (!lpc_dev) return 0; acpi_io_base = pci_read_config16(lpc_dev, 0x88); if (!acpi_io_base || (acpi_io_base & ~1) == 0) return 0; acpi_io_base &= ~1; gpio_in = inl(acpi_io_base + 0x48); /* bit 9 for primary port, clear if unconnected or 80-pin cable */ res = gpio_in & (1<<9) ? 0 : VT8237R_IDE0_80PIN_CABLE; /* bit 4 for secondary port, clear if unconnected or 80-pin cable */ res |= gpio_in & (1<<4) ? 0 : VT8237R_IDE1_80PIN_CABLE; printk(BIOS_INFO, "Cable on %s PATA port: %d pin\n", "primary", gpio_in & (1<<9) ? 40 : 80); printk(BIOS_INFO, "Cable on %s PATA port: %d pin\n", "secondary", gpio_in & (1<<4) ? 40 : 80); return res; }
unsigned long acpi_fill_mcfg(unsigned long current) { device_t dev; u32 pciexbar = 0; u32 pciexbar_reg; int max_buses; dev = dev_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_SB, 0); if (!dev) dev = dev_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_IB, 0); if (!dev) return current; pciexbar_reg=pci_read_config32(dev, PCIEXBAR); // MMCFG not supported or not enabled. if (!(pciexbar_reg & (1 << 0))) return current; switch ((pciexbar_reg >> 1) & 3) { case 0: // 256MB pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)); max_buses = 256; break; case 1: // 128M pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)); max_buses = 128; break; case 2: // 64M pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26)); max_buses = 64; break; default: // RSVD return current; } if (!pciexbar) return current; current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current, pciexbar, 0x0, 0x0, max_buses - 1); return current; }
static unsigned long get_memory_size(void) { device_t nb_dev; u8 size; nb_dev = dev_find_device(PCI_VENDOR_ID_RDC, PCI_DEVICE_ID_RDC_R8610_NB, 0); size = pci_read_config8(nb_dev, 0x6d) & 0xf; return (2 * 1024) << size; }
unsigned long acpi_fill_mcfg(unsigned long current) { device_t dev; struct resource *res; dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_K8T890CE_5, 0); if (!dev) dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_K8T890CF_5, 0); if (!dev) dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_K8M890CE_5, 0); if (!dev) return current; res = find_resource(dev, K8T890_MMCONFIG_MBAR); if (res) { current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current, res->base, 0x0, 0x0, 0xff); } return current; }
void pirq_assign_irqs(const unsigned char pIntAtoD[4]) { device_t pdev; pdev = dev_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, 0); if (pdev) { pci_write_config16(pdev, 0x5c, (pIntAtoD[3] << 12 | pIntAtoD[2] << 8 | pIntAtoD[1] << 4 | pIntAtoD[0])); } }
void pirq_assign_irqs(const unsigned char pIntAtoD[4]) { device_t pdev; pdev = dev_find_device(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5530_LEGACY, 0); if (pdev) { pci_write_config8(pdev, 0x5c, (pIntAtoD[1] << 4 | pIntAtoD[0])); pci_write_config8(pdev, 0x5d, (pIntAtoD[3] << 4 | pIntAtoD[2])); } }
static void pci_domain_set_resources(device_t dev) { device_t mc_dev; u32 pci_tolm; unsigned char reg; unsigned long tomk, tolmk; unsigned char rambits; int idx; pci_tolm = find_pci_tolm(dev->link_list); mc_dev = dev_find_device(PCI_VENDOR_ID_VIA, 0x3324, 0); rambits = pci_read_config8(mc_dev, 0x88); rambits >>= 2; /* Get memory size and frame buffer from northbridge's registers. * * If register contains an invalid value we set frame buffer size to a * default of 32M, but that probably won't happen. */ reg = pci_read_config8(mc_dev, 0xa1); reg &= 0x70; reg = reg >> 4; /* TOP 1M SMM Memory */ if (reg == 0x0 || reg == 0x6 || reg == 0x7) tomk = (((rambits << 6) - 32 - 1) * 1024); // Set frame buffer 32M for default else tomk = (((rambits << 6) - (4 << reg) - 1) * 1024); /* Compute the top of Low memory */ tolmk = pci_tolm >> 10; if (tolmk >= tomk) { /* The PCI hole does does not overlap the memory. */ tolmk = tomk; tolmk -= 1024; // TOP 1M SM Memory } #if CONFIG_WRITE_HIGH_TABLES == 1 high_tables_base = (tolmk * 1024) - HIGH_MEMORY_SIZE; high_tables_size = HIGH_MEMORY_SIZE; printk(BIOS_DEBUG, "tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n", tomk*1024, high_tables_base, high_tables_size); #endif /* Report the memory regions */ idx = 10; /* TODO: Hole needed? Should this go elsewhere? */ ram_resource(dev, idx++, 0, 640); /* first 640k */ ram_resource(dev, idx++, 768, (tolmk - 768)); /* leave a hole for vga */ assign_resources(dev->link_list); }
void variant_mainboard_final(void) { struct device *dev; uint16_t cmd = 0; /* Set Master Enable for on-board PCI device. */ dev = dev_find_device(PCI_VENDOR_ID_SIEMENS, 0x403e, 0); if (dev) { cmd = pci_read_config16(dev, PCI_COMMAND); cmd |= PCI_COMMAND_MASTER; pci_write_config16(dev, PCI_COMMAND, cmd); } }
void pirq_assign_irqs(const unsigned char route[4]) { device_t pdev; pdev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC, 0); if (!pdev) pdev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237S_LPC, 0); if (!pdev) pdev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237A_LPC, 0); if (!pdev) return; pci_write_config8(pdev, 0x55, route[0] << 4); pci_write_config8(pdev, 0x56, (route[2] << 4) | route[1]); pci_write_config8(pdev, 0x57, route[3] << 4); /* Enable INT[E-H] mapped to INT[A-D] for simplicity */ pci_write_config8(pdev, 0x46, 0x00); }
static void mainboard_init(device_t dev) { char **vpd_region_ptr = NULL; u32 search_length = find_fmap_entry("RO_VPD", (void **)vpd_region_ptr); u32 search_address = (unsigned long)(*vpd_region_ptr); u16 io_base = 0; struct device *ethernet_dev = NULL; /* Initialize the Embedded Controller */ butterfly_ec_init(); /* Program EC Keyboard locale based on VPD data */ program_keyboard_type(search_address, search_length); /* Get NIC's IO base address */ ethernet_dev = dev_find_device(BUTTERFLY_NIC_VENDOR_ID, BUTTERFLY_NIC_DEVICE_ID, dev); if (ethernet_dev != NULL) { io_base = pci_read_config16(ethernet_dev, 0x10) & 0xfffe; /* * Battery life time - LAN PCIe should enter ASPM L1 to save * power when LAN connection is idle. * enable CLKREQ: LAN pci config space 0x81h=01 */ pci_write_config8(ethernet_dev, 0x81, 0x01); } if (io_base) { /* Program MAC address based on VPD data */ program_mac_address(io_base, search_address, search_length); /* * Program NIC LEDS * * RTL8105E Series EEPROM-Less Application Note, * Section 5.6 LED Mode Configuration * * Step1: Write C0h to I/O register 0x50 via byte access to * disable 'register protection' * Step2: Write xx001111b to I/O register 0x52 via byte access * (bit7 is LEDS1 and bit6 is LEDS0) * Step3: Write 0x00 to I/O register 0x50 via byte access to * enable 'register protection' */ outb(0xc0, io_base + 0x50); /* Disable protection */ outb((BUTTERFLY_NIC_LED_MODE << 6) | 0x0f, io_base + 0x52); outb(0x00, io_base + 0x50); /* Enable register protection */ } }
static void write_protect_vgabios(void) { device_t dev; printk(BIOS_INFO, "write_protect_vgabios\n"); /* there are two possible devices. Just do both. */ dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VX855_MEMCTRL, 0); if (dev) pci_write_config8(dev, 0x80, 0xff); /*vx855 no th 0x61 reg */ /*dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VX855_VLINK, 0); //if(dev) // pci_write_config8(dev, 0x61, 0xff); */ }
static void hda_init(struct device *dev) { u8 byte; u32 dword; void *base; struct resource *res; u32 codec_mask; struct device *sm_dev; /* Enable azalia - PM_io 0x59[3], no ac97 in sb700. */ byte = pm_ioread(0x59); byte |= 1 << 3; pm_iowrite(0x59, byte); /* Find the SMBus */ sm_dev = dev_find_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SB700_SM, 0); /* Set routing pin - SMBus ExtFunc (0xf8/0xfc) */ pci_write_config32(sm_dev, 0xf8, 0x00); pci_write_config8(sm_dev, 0xfc, 0xAA); /* Set INTA - SMBus 0x63 [2..0] */ byte = pci_read_config8(sm_dev, 0x63); byte &= ~0x7; byte |= 0x0; /* INTA:0x0 - INTH:0x7 */ pci_write_config8(sm_dev, 0x63, byte); /* Program the 2C to 0x437b1002 */ dword = 0x437b1002; pci_write_config32(dev, 0x2c, dword); /* Read in BAR */ /* Is this right? HDA allows for a 64-bit BAR * but this is only setup for a 32-bit one */ res = find_resource(dev, 0x10); if (!res) return; base = res2mmio(res, 0, 0); printk(BIOS_DEBUG, "base = 0x%p\n", base); codec_mask = codec_detect(base); if (codec_mask) { printk(BIOS_DEBUG, "codec_mask = %02x\n", codec_mask); codecs_init(base, codec_mask); } }
static void mainboard_init(device_t dev) { device_t dev0, idedev, sdhci_dev; ec_clr_bit(0x03, 2); if (inb(0x164c) & 0x08) { ec_set_bit(0x03, 2); ec_write(0x0c, 0x88); } #if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE /* Install custom int15 handler for VGA OPROM */ mainboard_interrupt_handlers(0x15, &int15_handler); #endif /* If we're resuming from suspend, blink suspend LED */ dev0 = dev_find_slot(0, PCI_DEVFN(0,0)); if (dev0 && pci_read_config32(dev0, SKPAD) == SKPAD_ACPI_S3_MAGIC) ec_write(0x0c, 0xc7); idedev = dev_find_slot(0, PCI_DEVFN(0x1f,1)); if (idedev && idedev->chip_info && dock_ultrabay_device_present()) { struct southbridge_intel_i82801gx_config *config = idedev->chip_info; config->ide_enable_primary = 1; /* enable Ultrabay power */ outb(inb(0x1628) | 0x01, 0x1628); ec_write(0x0c, 0x84); } else { /* disable Ultrabay power */ outb(inb(0x1628) & ~0x01, 0x1628); ec_write(0x0c, 0x04); } /* Set SDHCI write protect polarity "SDWPPol" */ sdhci_dev = dev_find_device(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C822, 0); if (sdhci_dev) { if (pci_read_config8(sdhci_dev, 0xfa) != 0x20) { /* unlock */ pci_write_config8(sdhci_dev, 0xf9, 0xfc); /* set SDWPPol, keep CLKRUNDis, SDPWRPol clear */ pci_write_config8(sdhci_dev, 0xfa, 0x20); /* restore lock */ pci_write_config8(sdhci_dev, 0xf9, 0x00); } } }
unsigned long acpi_fill_mcfg(unsigned long current) { device_t dev; u32 reg; dev = dev_find_device(0x8086, 0x29c0, 0); if (!dev) return current; reg = pci_read_config32(dev, 0x60); if ((reg & 0x07) != 0x01) // require enabled + 256MB size return current; current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current, reg & 0xf0000000, 0x0, 0x0, 255); return current; }
unsigned long acpi_fill_mcfg(unsigned long current) { device_t dev; u32 pciexbar = 0; u32 pciexbar_reg; int max_buses; dev = dev_find_device(0x8086, 0x27a0, 0); if (!dev) return current; pciexbar_reg = pci_read_config32(dev, 0x48); /* MMCFG not supported or not enabled. */ if (!(pciexbar_reg & (1 << 0))) return current; switch ((pciexbar_reg >> 1) & 3) { case 0: /* 256MB */ pciexbar = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) | (1 << 28)); max_buses = 256; break; case 1: /* 128M */ pciexbar = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) | (1 << 28) | (1 << 27)); max_buses = 128; break; case 2: /* 64M */ pciexbar = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) | (1 << 28) | (1 << 27) | (1 << 26)); max_buses = 64; break; default: /* RSVD */ return current; } if (!pciexbar) return current; #if CONFIG_GENERATE_ACPI_TABLES current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current, pciexbar, 0x0, 0x0, max_buses - 1); #endif return current; }
static void mainboard_init(device_t dev) { struct device *ethernet_dev = NULL; /* Initialize the Embedded Controller */ stout_ec_init(); /* * Battery life time - LAN PCIe should enter ASPM L1 to save * power when LAN connection is idle. * enable CLKREQ: LAN pci config space 0x81h=01 */ ethernet_dev = dev_find_device(STOUT_NIC_VENDOR_ID, STOUT_NIC_DEVICE_ID, dev); if (ethernet_dev != NULL) pci_write_config8(ethernet_dev, 0x81, 0x01); }
void pirq_assign_irqs(const u8 * pirq) { device_t lpc; lpc = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VX900_LPC, 0); /* Take care of INTA -> INTD */ pci_mod_config8(lpc, 0x55, (0xf << 4), pirq[0] << 4); pci_write_config8(lpc, 0x56, pirq[1] | (pirq[2] << 4)); pci_write_config8(lpc, 0x57, pirq[3] << 4); /* Enable INTE -> INTH to be on separate IRQs */ pci_mod_config8(lpc, 0x46, 0, 1 << 4); /* Now do INTE -> INTH */ pci_write_config8(lpc, 0x44, pirq[4] | (pirq[5] << 4)); pci_write_config8(lpc, 0x45, pirq[6] | (pirq[7] << 4)); }
static void mainboard_init(device_t dev) { device_t dev0, idedev, sdhci_dev; ec_clr_bit(0x03, 2); if (inb(0x164c) & 0x08) { ec_set_bit(0x03, 2); ec_write(0x0c, 0x88); } install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, PANEL, 3); /* If we're resuming from suspend, blink suspend LED */ dev0 = dev_find_slot(0, PCI_DEVFN(0,0)); if (dev0 && pci_read_config32(dev0, SKPAD) == SKPAD_ACPI_S3_MAGIC) ec_write(0x0c, 0xc7); idedev = dev_find_slot(0, PCI_DEVFN(0x1f,1)); if (idedev && idedev->chip_info && dock_ultrabay_device_present()) { struct southbridge_intel_i82801gx_config *config = idedev->chip_info; config->ide_enable_primary = 1; /* enable Ultrabay power */ outb(inb(0x1628) | 0x01, 0x1628); ec_write(0x0c, 0x84); } else { /* disable Ultrabay power */ outb(inb(0x1628) & ~0x01, 0x1628); ec_write(0x0c, 0x04); } /* Set SDHCI write protect polarity "SDWPPol" */ sdhci_dev = dev_find_device(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C822, 0); if (sdhci_dev) { if (pci_read_config8(sdhci_dev, 0xfa) != 0x20) { /* unlock */ pci_write_config8(sdhci_dev, 0xf9, 0xfc); /* set SDWPPol, keep CLKRUNDis, SDPWRPol clear */ pci_write_config8(sdhci_dev, 0xfa, 0x20); /* restore lock */ pci_write_config8(sdhci_dev, 0xf9, 0x00); } } }
void lan_init(void) { u16 io_base = 0; struct device *ethernet_dev = NULL; /* Get NIC's IO base address */ ethernet_dev = dev_find_device(JECHT_NIC_VENDOR_ID, JECHT_NIC_DEVICE_ID, 0); if (ethernet_dev != NULL) { io_base = pci_read_config16(ethernet_dev, 0x10) & 0xfffe; /* * Battery life time - LAN PCIe should enter ASPM L1 to save * power when LAN connection is idle. * enable CLKREQ: LAN pci config space 0x81h=01 */ pci_write_config8(ethernet_dev, 0x81, 0x01); } if (io_base) { /* Program MAC address based on VPD data */ program_mac_address(io_base); /* * Program NIC LEDS * * RTL8105E Series EEPROM-Less Application Note, * Section 5.6 LED Mode Configuration * * Step1: Write C0h to I/O register 0x50 via byte access to * disable 'register protection' * Step2: Write xx001111b to I/O register 0x52 via byte access * (bit7 is LEDS1 and bit6 is LEDS0) * Step3: Write 0x00 to I/O register 0x50 via byte access to * enable 'register protection' */ outb(0xc0, io_base + 0x50); /* Disable protection */ outb((JECHT_NIC_LED_MODE << 6) | 0x0f, io_base + 0x52); outb(0x00, io_base + 0x50); /* Enable register protection */ } }
unsigned long acpi_fill_mcfg(unsigned long current) { device_t dev; u64 mmcfg; dev = dev_find_device(0x1106, 0x324b, 0); // 0:0x13.0 if (!dev) return current; // MMCFG not supported or not enabled. if ((pci_read_config8(dev, 0x40) & 0xC0) != 0xC0) return current; mmcfg = ((u64) pci_read_config8(dev, 0x41)) << 28; if (!mmcfg) return current; current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current, mmcfg, 0x0, 0x0, 0xff); return current; }
static void ctrl_init(struct device *dev) { /* TODO: Fix some ordering issue fo V-link set Rx77[6] and PCI1_Rx4F[0] should to 1 */ /* C2P Read ACK Return Priority */ /* PCI CFG Address bits[27:24] are used as extended register address bit[11:8] */ pci_write_config8(dev, 0x47, 0x30); /* VT8237R specific configuration other SB are done in their own directories */ device_t devsb = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC, 0); if (devsb) { vt8237r_vlink_init(dev); vt8237r_cfg(dev, devsb); } }