/**
* The BPMP exposes multiple different services. We create a sub-device for
* each separate type of service, since each device must be of the appropriate
* UCLASS.
*/
static int tegra186_bpmp_bind(struct udevice *dev)
{
int ret;
struct udevice *child;
debug("%s(dev=%p)\n", __func__, dev);
ret = device_bind_driver_to_node(dev, "tegra186_clk", "tegra186_clk",
dev_of_offset(dev), &child);
if (ret)
return ret;
ret = device_bind_driver_to_node(dev, "tegra186_reset",
"tegra186_reset", dev_of_offset(dev),
&child);
if (ret)
return ret;
ret = device_bind_driver_to_node(dev, "tegra186_power_domain",
"tegra186_power_domain",
dev_of_offset(dev), &child);
if (ret)
return ret;
ret = dm_scan_fdt_dev(dev);
if (ret)
return ret;
return 0;
}
static int ftsdc010_mmc_ofdata_to_platdata(struct udevice *dev)
{
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
struct ftsdc_priv *priv = dev_get_priv(dev);
struct ftsdc010_chip *chip = &priv->chip;
chip->name = dev->name;
chip->ioaddr = (void *)devfdt_get_addr(dev);
chip->buswidth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
"bus-width", 4);
chip->priv = dev;
priv->fifo_depth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
"fifo-depth", 0);
priv->fifo_mode = fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev),
"fifo-mode");
if (fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev),
"clock-freq-min-max", priv->minmax, 2)) {
int val = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
"max-frequency", -EINVAL);
if (val < 0)
return val;
priv->minmax[0] = 400000; /* 400 kHz */
priv->minmax[1] = val;
} else {
debug("%s: 'clock-freq-min-max' property was deprecated.\n",
__func__);
}
#endif
chip->sclk = priv->minmax[1];
chip->regs = chip->ioaddr;
return 0;
}
static int emaclite_ofdata_to_platdata(struct udevice *dev)
{
struct eth_pdata *pdata = dev_get_platdata(dev);
struct xemaclite *emaclite = dev_get_priv(dev);
int offset = 0;
pdata->iobase = (phys_addr_t)devfdt_get_addr(dev);
emaclite->regs = (struct emaclite_regs *)ioremap_nocache(pdata->iobase,
0x10000);
emaclite->phyaddr = -1;
offset = fdtdec_lookup_phandle(gd->fdt_blob, dev_of_offset(dev),
"phy-handle");
if (offset > 0)
emaclite->phyaddr = fdtdec_get_int(gd->fdt_blob, offset,
"reg", -1);
emaclite->txpp = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
"xlnx,tx-ping-pong", 0);
emaclite->rxpp = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
"xlnx,rx-ping-pong", 0);
printf("EMACLITE: %lx, phyaddr %d, %d/%d\n", (ulong)emaclite->regs,
emaclite->phyaddr, emaclite->txpp, emaclite->rxpp);
return 0;
}
static int zynqmp_qspi_ofdata_to_platdata(struct udevice *bus)
{
struct zynqmp_qspi_platdata *plat = bus->platdata;
int is_dual;
debug("%s\n", __func__);
plat->regs = (struct zynqmp_qspi_regs *)(devfdt_get_addr(bus) +
GQSPI_REG_OFFSET);
plat->dma_regs = (struct zynqmp_qspi_dma_regs *)
(devfdt_get_addr(bus) + GQSPI_DMA_REG_OFFSET);
is_dual = fdtdec_get_int(gd->fdt_blob, dev_of_offset(bus), "is-dual", -1);
if (is_dual < 0)
plat->is_dual = SF_SINGLE_FLASH;
else if (is_dual == 1)
plat->is_dual = SF_DUAL_PARALLEL_FLASH;
else
if (fdtdec_get_int(gd->fdt_blob, dev_of_offset(bus),
"is-stacked", -1) < 0)
plat->is_dual = SF_SINGLE_FLASH;
else
plat->is_dual = SF_DUAL_STACKED_FLASH;
plat->io_mode = fdtdec_get_bool(gd->fdt_blob, dev_of_offset(bus),
"has-io-mode");
return 0;
}
static int atmel_hlcdc_ofdata_to_platdata(struct udevice *dev)
{
struct atmel_hlcdc_priv *priv = dev_get_priv(dev);
const void *blob = gd->fdt_blob;
int node = dev_of_offset(dev);
priv->regs = (struct atmel_hlcd_regs *)devfdt_get_addr(dev);
if (!priv->regs) {
debug("%s: No display controller address\n", __func__);
return -EINVAL;
}
if (fdtdec_decode_display_timing(blob, dev_of_offset(dev),
0, &priv->timing)) {
debug("%s: Failed to decode display timing\n", __func__);
return -EINVAL;
}
if (priv->timing.hactive.typ > LCD_MAX_WIDTH)
priv->timing.hactive.typ = LCD_MAX_WIDTH;
if (priv->timing.vactive.typ > LCD_MAX_HEIGHT)
priv->timing.vactive.typ = LCD_MAX_HEIGHT;
priv->vl_bpix = fdtdec_get_int(blob, node, "atmel,vl-bpix", 0);
if (!priv->vl_bpix) {
debug("%s: Failed to get bits per pixel\n", __func__);
return -EINVAL;
}
priv->output_mode = fdtdec_get_int(blob, node, "atmel,output-mode", 24);
priv->guard_time = fdtdec_get_int(blob, node, "atmel,guard-time", 1);
return 0;
}
static int msm_spmi_probe(struct udevice *dev)
{
struct udevice *parent = dev->parent;
struct msm_spmi_priv *priv = dev_get_priv(dev);
int node = dev_of_offset(dev);
int i;
priv->arb_chnl = devfdt_get_addr(dev);
priv->spmi_core = fdtdec_get_addr_size_auto_parent(gd->fdt_blob,
dev_of_offset(parent), node, "reg", 1, NULL, false);
priv->spmi_obs = fdtdec_get_addr_size_auto_parent(gd->fdt_blob,
dev_of_offset(parent), node, "reg", 2, NULL, false);
if (priv->arb_chnl == FDT_ADDR_T_NONE ||
priv->spmi_core == FDT_ADDR_T_NONE ||
priv->spmi_obs == FDT_ADDR_T_NONE)
return -EINVAL;
/* Scan peripherals connected to each SPMI channel */
for (i = 0; i < SPMI_MAX_CHANNELS ; i++) {
uint32_t periph = readl(priv->arb_chnl + ARB_CHANNEL_OFFSET(i));
uint8_t slave_id = (periph & 0xf0000) >> 16;
uint8_t pid = (periph & 0xff00) >> 8;
priv->channel_map[slave_id][pid] = i;
}
return 0;
}
/**
* dp83867_data_init - Convenience function for setting PHY specific data
*
* @phydev: the phy_device struct
*/
static int dp83867_of_init(struct phy_device *phydev)
{
struct dp83867_private *dp83867 = phydev->priv;
struct udevice *dev = phydev->dev;
int node = dev_of_offset(dev);
const void *fdt = gd->fdt_blob;
if (fdtdec_get_bool(fdt, node, "ti,max-output-impedance"))
dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX;
else if (fdtdec_get_bool(fdt, node, "ti,min-output-impedance"))
dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN;
else
dp83867->io_impedance = -EINVAL;
dp83867->rx_id_delay = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
"ti,rx-internal-delay", -1);
dp83867->tx_id_delay = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
"ti,tx-internal-delay", -1);
dp83867->fifo_depth = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
"ti,fifo-depth", -1);
return 0;
}
int syscon_reboot_probe(struct udevice *dev)
{
struct udevice *syscon;
struct syscon_reboot_priv *priv = dev_get_priv(dev);
int err;
err = uclass_get_device_by_phandle(UCLASS_SYSCON, dev,
"regmap", &syscon);
if (err) {
error("unable to find syscon device\n");
return err;
}
priv->regmap = syscon_get_regmap(syscon);
if (!priv->regmap) {
error("unable to find regmap\n");
return -ENODEV;
}
priv->offset = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
"offset", 0);
priv->mask = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
"mask", 0);
return 0;
}
int dm_check_devices(struct unit_test_state *uts, int num_devices)
{
struct udevice *dev;
int ret;
int i;
/*
* Now check that the ping adds are what we expect. This is using the
* ping-add property in each node.
*/
for (i = 0; i < num_devices; i++) {
uint32_t base;
ret = uclass_get_device(UCLASS_TEST_FDT, i, &dev);
ut_assert(!ret);
/*
* Get the 'ping-expect' property, which tells us what the
* ping add should be. We don't use the platdata because we
* want to test the code that sets that up
* (testfdt_drv_probe()).
*/
base = fdtdec_get_addr(gd->fdt_blob, dev_of_offset(dev),
"ping-expect");
debug("dev=%d, base=%d: %s\n", i, base,
fdt_get_name(gd->fdt_blob, dev_of_offset(dev), NULL));
ut_assert(!dm_check_operations(uts, dev, base,
dev_get_priv(dev)));
}
return 0;
}
static int testfdt_ofdata_to_platdata(struct udevice *dev)
{
struct dm_test_pdata *pdata = dev_get_platdata(dev);
pdata->ping_add = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
"ping-add", -1);
pdata->base = fdtdec_get_addr(gd->fdt_blob, dev_of_offset(dev),
"ping-expect");
return 0;
}
static int gpio_dwapb_bind(struct udevice *dev)
{
struct gpio_dwapb_platdata *plat = dev_get_platdata(dev);
const void *blob = gd->fdt_blob;
struct udevice *subdev;
fdt_addr_t base;
int ret, node, bank = 0;
/* If this is a child device, there is nothing to do here */
if (plat)
return 0;
base = fdtdec_get_addr(blob, dev_of_offset(dev), "reg");
if (base == FDT_ADDR_T_NONE) {
debug("Can't get the GPIO register base address\n");
return -ENXIO;
}
for (node = fdt_first_subnode(blob, dev_of_offset(dev));
node > 0;
node = fdt_next_subnode(blob, node)) {
if (!fdtdec_get_bool(blob, node, "gpio-controller"))
continue;
plat = NULL;
plat = calloc(1, sizeof(*plat));
if (!plat)
return -ENOMEM;
plat->base = base;
plat->bank = bank;
plat->pins = fdtdec_get_int(blob, node, "snps,nr-gpios", 0);
plat->name = fdt_stringlist_get(blob, node, "bank-name", 0,
NULL);
if (ret)
goto err;
ret = device_bind(dev, dev->driver, plat->name,
plat, -1, &subdev);
if (ret)
goto err;
dev_set_of_offset(subdev, node);
bank++;
}
return 0;
err:
free(plat);
return ret;
}
int cros_ec_probe(struct udevice *dev)
{
struct ec_state *ec = dev->priv;
struct cros_ec_dev *cdev = dev->uclass_priv;
const void *blob = gd->fdt_blob;
struct udevice *keyb_dev;
int node;
int err;
memcpy(ec, &s_state, sizeof(*ec));
err = cros_ec_decode_ec_flash(blob, dev_of_offset(dev), &ec->ec_config);
if (err)
return err;
node = -1;
for (device_find_first_child(dev, &keyb_dev);
keyb_dev;
device_find_next_child(&keyb_dev)) {
if (device_get_uclass_id(keyb_dev) == UCLASS_KEYBOARD) {
node = dev_of_offset(keyb_dev);
break;
}
}
if (node < 0) {
debug("%s: No cros_ec keyboard found\n", __func__);
} else if (keyscan_read_fdt_matrix(ec, blob, node)) {
debug("%s: Could not read key matrix\n", __func__);
return -1;
}
/* If we loaded EC data, check that the length matches */
if (ec->flash_data &&
ec->flash_data_len != ec->ec_config.flash.length) {
printf("EC data length is %x, expected %x, discarding data\n",
ec->flash_data_len, ec->ec_config.flash.length);
os_free(ec->flash_data);
ec->flash_data = NULL;
}
/* Otherwise allocate the memory */
if (!ec->flash_data) {
ec->flash_data_len = ec->ec_config.flash.length;
ec->flash_data = os_malloc(ec->flash_data_len);
if (!ec->flash_data)
return -ENOMEM;
}
cdev->dev = dev;
g_state = ec;
return cros_ec_register(dev);
}
static int pic32_eth_probe(struct udevice *dev)
{
struct eth_pdata *pdata = dev_get_platdata(dev);
struct pic32eth_dev *priv = dev_get_priv(dev);
const char *phy_mode;
void __iomem *iobase;
fdt_addr_t addr;
fdt_size_t size;
int offset = 0;
int phy_addr = -1;
addr = fdtdec_get_addr_size(gd->fdt_blob, dev_of_offset(dev), "reg",
&size);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
iobase = ioremap(addr, size);
pdata->iobase = (phys_addr_t)addr;
/* get phy mode */
pdata->phy_interface = -1;
phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
NULL);
if (phy_mode)
pdata->phy_interface = phy_get_interface_by_name(phy_mode);
if (pdata->phy_interface == -1) {
debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
return -EINVAL;
}
/* get phy addr */
offset = fdtdec_lookup_phandle(gd->fdt_blob, dev_of_offset(dev),
"phy-handle");
if (offset > 0)
phy_addr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1);
/* phy reset gpio */
gpio_request_by_name_nodev(dev_ofnode(dev), "reset-gpios", 0,
&priv->rst_gpio, GPIOD_IS_OUT);
priv->phyif = pdata->phy_interface;
priv->phy_addr = phy_addr;
priv->ectl_regs = iobase;
priv->emac_regs = iobase + PIC32_EMAC1CFG1;
pic32_mii_init(priv);
return pic32_phy_init(priv, dev);
}
static int simple_video_probe(struct udevice *dev)
{
struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
struct video_priv *uc_priv = dev_get_uclass_priv(dev);
const void *blob = gd->fdt_blob;
const int node = dev_of_offset(dev);
const char *format;
fdt_addr_t base;
fdt_size_t size;
base = fdtdec_get_addr_size_auto_parent(blob, dev_of_offset(dev->parent),
node, "reg", 0, &size, false);
if (base == FDT_ADDR_T_NONE) {
debug("%s: Failed to decode memory region\n", __func__);
return -EINVAL;
}
debug("%s: base=%llx, size=%llu\n", __func__, base, size);
/*
* TODO is there some way to reserve the framebuffer
* region so it isn't clobbered?
*/
plat->base = base;
plat->size = size;
video_set_flush_dcache(dev, true);
debug("%s: Query resolution...\n", __func__);
uc_priv->xsize = fdtdec_get_uint(blob, node, "width", 0);
uc_priv->ysize = fdtdec_get_uint(blob, node, "height", 0);
uc_priv->rot = 0;
format = fdt_getprop(blob, node, "format", NULL);
debug("%s: %dx%d@%s\n", __func__, uc_priv->xsize, uc_priv->ysize, format);
if (strcmp(format, "r5g6b5") == 0) {
uc_priv->bpix = VIDEO_BPP16;
} else if (strcmp(format, "a8b8g8r8") == 0) {
uc_priv->bpix = VIDEO_BPP32;
} else {
printf("%s: invalid format: %s\n", __func__, format);
return -EINVAL;
}
return 0;
}
static int zynq_gem_ofdata_to_platdata(struct udevice *dev)
{
struct eth_pdata *pdata = dev_get_platdata(dev);
struct zynq_gem_priv *priv = dev_get_priv(dev);
int node = dev_of_offset(dev);
const char *phy_mode;
pdata->iobase = (phys_addr_t)dev_get_addr(dev);
priv->iobase = (struct zynq_gem_regs *)pdata->iobase;
/* Hardcode for now */
priv->emio = 0;
priv->phyaddr = -1;
priv->phy_of_handle = fdtdec_lookup_phandle(gd->fdt_blob, node,
"phy-handle");
if (priv->phy_of_handle > 0)
priv->phyaddr = fdtdec_get_int(gd->fdt_blob,
priv->phy_of_handle, "reg", -1);
phy_mode = fdt_getprop(gd->fdt_blob, node, "phy-mode", NULL);
if (phy_mode)
pdata->phy_interface = phy_get_interface_by_name(phy_mode);
if (pdata->phy_interface == -1) {
debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
return -EINVAL;
}
priv->interface = pdata->phy_interface;
priv->emio = fdtdec_get_bool(gd->fdt_blob, node, "xlnx,emio");
printf("ZYNQ GEM: %lx, phyaddr %x, interface %s\n", (ulong)priv->iobase,
priv->phyaddr, phy_string_for_interface(priv->interface));
return 0;
}
static int altera_nios2_probe(struct udevice *dev)
{
const void *blob = gd->fdt_blob;
int node = dev_of_offset(dev);
gd->cpu_clk = fdtdec_get_int(blob, node,
"clock-frequency", 0);
gd->arch.dcache_line_size = fdtdec_get_int(blob, node,
"dcache-line-size", 0);
gd->arch.icache_line_size = fdtdec_get_int(blob, node,
"icache-line-size", 0);
gd->arch.dcache_size = fdtdec_get_int(blob, node,
"dcache-size", 0);
gd->arch.icache_size = fdtdec_get_int(blob, node,
"icache-size", 0);
gd->arch.reset_addr = fdtdec_get_int(blob, node,
"altr,reset-addr", 0);
gd->arch.exception_addr = fdtdec_get_int(blob, node,
"altr,exception-addr", 0);
gd->arch.has_initda = fdtdec_get_int(blob, node,
"altr,has-initda", 0);
gd->arch.has_mmu = fdtdec_get_int(blob, node,
"altr,has-mmu", 0);
gd->arch.io_region_base = gd->arch.has_mmu ? 0xe0000000 : 0x80000000;
gd->arch.mem_region_base = gd->arch.has_mmu ? 0xc0000000 : 0x00000000;
gd->arch.physaddr_mask = gd->arch.has_mmu ? 0x1fffffff : 0x7fffffff;
return 0;
}
/**
* We have a top-level GPIO device with no actual GPIOs. It has a child
* device for each Sunxi bank.
*/
static int gpio_sunxi_bind(struct udevice *parent)
{
struct sunxi_gpio_soc_data *soc_data =
(struct sunxi_gpio_soc_data *)dev_get_driver_data(parent);
struct sunxi_gpio_platdata *plat = parent->platdata;
struct sunxi_gpio_reg *ctlr;
int bank, ret;
/* If this is a child device, there is nothing to do here */
if (plat)
return 0;
ctlr = (struct sunxi_gpio_reg *)devfdt_get_addr(parent);
for (bank = 0; bank < soc_data->no_banks; bank++) {
struct sunxi_gpio_platdata *plat;
struct udevice *dev;
plat = calloc(1, sizeof(*plat));
if (!plat)
return -ENOMEM;
plat->regs = &ctlr->gpio_bank[bank];
plat->bank_name = gpio_bank_name(soc_data->start + bank);
plat->gpio_count = SUNXI_GPIOS_PER_BANK;
ret = device_bind(parent, parent->driver,
plat->bank_name, plat, -1, &dev);
if (ret)
return ret;
dev_set_of_offset(dev, dev_of_offset(parent));
}
return 0;
}
static int rk3188_pinctrl_set_state(struct udevice *dev, struct udevice *config)
{
const void *blob = gd->fdt_blob;
int pcfg_node, ret, flags, count, i;
u32 cell[60], *ptr;
debug("%s: %s %s\n", __func__, dev->name, config->name);
ret = fdtdec_get_int_array_count(blob, dev_of_offset(config),
"rockchip,pins", cell,
ARRAY_SIZE(cell));
if (ret < 0) {
debug("%s: bad array %d\n", __func__, ret);
return -EINVAL;
}
count = ret;
for (i = 0, ptr = cell; i < count; i += 4, ptr += 4) {
pcfg_node = fdt_node_offset_by_phandle(blob, ptr[3]);
if (pcfg_node < 0)
return -EINVAL;
flags = pinctrl_decode_pin_config(blob, pcfg_node);
if (flags < 0)
return flags;
ret = rk3188_pinctrl_set_pins(dev, ptr[0], ptr[1], ptr[2],
flags);
if (ret)
return ret;
}
return 0;
}
static int led_gpio_bind(struct udevice *parent)
{
const void *blob = gd->fdt_blob;
struct udevice *dev;
int node;
int ret;
for (node = fdt_first_subnode(blob, dev_of_offset(parent));
node > 0;
node = fdt_next_subnode(blob, node)) {
struct led_uclass_plat *uc_plat;
const char *label;
label = fdt_getprop(blob, node, "label", NULL);
if (!label) {
debug("%s: node %s has no label\n", __func__,
fdt_get_name(blob, node, NULL));
return -EINVAL;
}
ret = device_bind_driver_to_node(parent, "gpio_led",
fdt_get_name(blob, node, NULL),
node, &dev);
if (ret)
return ret;
uc_plat = dev_get_uclass_platdata(dev);
uc_plat->label = label;
}
return 0;
}
static int tegra20_sflash_ofdata_to_platdata(struct udevice *bus)
{
struct tegra_spi_platdata *plat = bus->platdata;
const void *blob = gd->fdt_blob;
int node = dev_of_offset(bus);
plat->base = devfdt_get_addr(bus);
plat->periph_id = clock_decode_periph_id(bus);
if (plat->periph_id == PERIPH_ID_NONE) {
debug("%s: could not decode periph id %d\n", __func__,
plat->periph_id);
return -FDT_ERR_NOTFOUND;
}
/* Use 500KHz as a suitable default */
plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
500000);
plat->deactivate_delay_us = fdtdec_get_int(blob, node,
"spi-deactivate-delay", 0);
debug("%s: base=%#08lx, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n",
__func__, plat->base, plat->periph_id, plat->frequency,
plat->deactivate_delay_us);
return 0;
}
static int xenon_sdhci_ofdata_to_platdata(struct udevice *dev)
{
struct sdhci_host *host = dev_get_priv(dev);
struct xenon_sdhci_priv *priv = dev_get_priv(dev);
const char *name;
host->name = dev->name;
host->ioaddr = (void *)devfdt_get_addr(dev);
if (device_is_compatible(dev, "marvell,armada-3700-sdhci"))
priv->pad_ctrl_reg = (void *)devfdt_get_addr_index(dev, 1);
name = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "marvell,pad-type",
NULL);
if (name) {
if (0 == strncmp(name, "sd", 2)) {
priv->pad_type = SOC_PAD_SD;
} else if (0 == strncmp(name, "fixed-1-8v", 10)) {
priv->pad_type = SOC_PAD_FIXED_1_8V;
} else {
printf("Unsupported SOC PHY PAD ctrl type %s\n", name);
return -EINVAL;
}
}
return 0;
}
/* Check for vol- button - if pressed - stop autoboot */
int misc_init_r(void)
{
struct udevice *pon;
struct gpio_desc resin;
int node, ret;
ret = uclass_get_device_by_name(UCLASS_GPIO, "pm8916_pon@800", &pon);
if (ret < 0) {
printf("Failed to find PMIC pon node. Check device tree\n");
return 0;
}
node = fdt_subnode_offset(gd->fdt_blob, dev_of_offset(pon),
"key_vol_down");
if (node < 0) {
printf("Failed to find key_vol_down node. Check device tree\n");
return 0;
}
if (gpio_request_by_name_nodev(offset_to_ofnode(node), "gpios", 0,
&resin, 0)) {
printf("Failed to request key_vol_down button.\n");
return 0;
}
if (dm_gpio_get_value(&resin)) {
env_set("bootdelay", "-1");
printf("Power button pressed - dropping to console.\n");
}
return 0;
}
static int pwm_regulator_ofdata_to_platdata(struct udevice *dev)
{
struct pwm_regulator_info *priv = dev_get_priv(dev);
struct fdtdec_phandle_args args;
const void *blob = gd->fdt_blob;
int node = dev_of_offset(dev);
int ret;
ret = fdtdec_parse_phandle_with_args(blob, node, "pwms", "#pwm-cells",
0, 0, &args);
if (ret) {
debug("%s: Cannot get PWM phandle: ret=%d\n", __func__, ret);
return ret;
}
priv->period_ns = args.args[1];
priv->polarity = args.args[2];
priv->init_voltage = fdtdec_get_int(blob, node,
"regulator-init-microvolt", -1);
if (priv->init_voltage < 0) {
printf("Cannot find regulator pwm init_voltage\n");
return -EINVAL;
}
ret = uclass_get_device_by_of_offset(UCLASS_PWM, args.node, &priv->pwm);
if (ret) {
debug("%s: Cannot get PWM: ret=%d\n", __func__, ret);
return ret;
}
return 0;
}
static int pic32_pinctrl_probe(struct udevice *dev)
{
struct pic32_pinctrl_priv *priv = dev_get_priv(dev);
struct fdt_resource res;
void *fdt = (void *)gd->fdt_blob;
int node = dev_of_offset(dev);
int ret;
ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
"ppsin", &res);
if (ret < 0) {
printf("pinctrl: resource \"ppsin\" not found\n");
return ret;
}
priv->mux_in = ioremap(res.start, fdt_resource_size(&res));
ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
"ppsout", &res);
if (ret < 0) {
printf("pinctrl: resource \"ppsout\" not found\n");
return ret;
}
priv->mux_out = ioremap(res.start, fdt_resource_size(&res));
ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
"port", &res);
if (ret < 0) {
printf("pinctrl: resource \"port\" not found\n");
return ret;
}
priv->pinconf = ioremap(res.start, fdt_resource_size(&res));
return 0;
}
static int ti_qspi_ofdata_to_platdata(struct udevice *bus)
{
struct ti_qspi_priv *priv = dev_get_priv(bus);
const void *blob = gd->fdt_blob;
int node = dev_of_offset(bus);
fdt_addr_t mmap_addr;
fdt_addr_t mmap_size;
priv->ctrl_mod_mmap = map_syscon_chipselects(bus);
priv->base = map_physmem(devfdt_get_addr(bus),
sizeof(struct ti_qspi_regs), MAP_NOCACHE);
mmap_addr = devfdt_get_addr_size_index(bus, 1, &mmap_size);
priv->memory_map = map_physmem(mmap_addr, mmap_size, MAP_NOCACHE);
priv->mmap_size = mmap_size;
priv->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", -1);
if (priv->max_hz < 0) {
debug("Error: Max frequency missing\n");
return -ENODEV;
}
priv->num_cs = fdtdec_get_int(blob, node, "num-cs", 4);
debug("%s: regs=<0x%x>, max-frequency=%d\n", __func__,
(int)priv->base, priv->max_hz);
return 0;
}
static int rcar_gpio_probe(struct udevice *dev)
{
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
struct rcar_gpio_priv *priv = dev_get_priv(dev);
struct fdtdec_phandle_args args;
struct clk clk;
int node = dev_of_offset(dev);
int ret;
priv->regs = (void __iomem *)devfdt_get_addr(dev);
uc_priv->bank_name = dev->name;
ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, node, "gpio-ranges",
NULL, 3, 0, &args);
uc_priv->gpio_count = ret == 0 ? args.args[2] : RCAR_MAX_GPIO_PER_BANK;
ret = clk_get_by_index(dev, 0, &clk);
if (ret < 0) {
dev_err(dev, "Failed to get GPIO bank clock\n");
return ret;
}
ret = clk_enable(&clk);
clk_free(&clk);
if (ret) {
dev_err(dev, "Failed to enable GPIO bank clock\n");
return ret;
}
return 0;
}
static int pic32_uart_probe(struct udevice *dev)
{
struct pic32_uart_priv *priv = dev_get_priv(dev);
struct clk clk;
fdt_addr_t addr;
fdt_size_t size;
int ret;
/* get address */
addr = fdtdec_get_addr_size(gd->fdt_blob, dev_of_offset(dev), "reg",
&size);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
priv->base = ioremap(addr, size);
/* get clock rate */
ret = clk_get_by_index(dev, 0, &clk);
if (ret < 0)
return ret;
priv->uartclk = clk_get_rate(&clk);
clk_free(&clk);
/* initialize serial */
return pic32_serial_init(priv->base, priv->uartclk, CONFIG_BAUDRATE);
}
static int pcie_intel_fpga_ofdata_to_platdata(struct udevice *dev)
{
struct intel_fpga_pcie *pcie = dev_get_priv(dev);
struct fdt_resource reg_res;
int node = dev_of_offset(dev);
int ret;
DECLARE_GLOBAL_DATA_PTR;
ret = fdt_get_named_resource(gd->fdt_blob, node, "reg", "reg-names",
"Cra", ®_res);
if (ret) {
dev_err(dev, "resource \"Cra\" not found\n");
return ret;
}
pcie->cra_base = map_physmem(reg_res.start,
fdt_resource_size(®_res),
MAP_NOCACHE);
ret = fdt_get_named_resource(gd->fdt_blob, node, "reg", "reg-names",
"Hip", ®_res);
if (ret) {
dev_err(dev, "resource \"Hip\" not found\n");
return ret;
}
pcie->hip_base = map_physmem(reg_res.start,
fdt_resource_size(®_res),
MAP_NOCACHE);
return 0;
}
int pmic_bind_children(struct udevice *pmic, ofnode parent,
const struct pmic_child_info *child_info)
{
const struct pmic_child_info *info;
struct driver *drv;
struct udevice *child;
const char *node_name;
int bind_count = 0;
ofnode node;
int prefix_len;
int ret;
debug("%s for '%s' at node offset: %d\n", __func__, pmic->name,
dev_of_offset(pmic));
ofnode_for_each_subnode(node, parent) {
node_name = ofnode_get_name(node);
debug("* Found child node: '%s'\n", node_name);
child = NULL;
for (info = child_info; info->prefix && info->driver; info++) {
debug(" - compatible prefix: '%s'\n", info->prefix);
prefix_len = strlen(info->prefix);
if (strncmp(info->prefix, node_name, prefix_len))
continue;
drv = lists_driver_lookup_name(info->driver);
if (!drv) {
debug(" - driver: '%s' not found!\n",
info->driver);
continue;
}
debug(" - found child driver: '%s'\n", drv->name);
ret = device_bind_with_driver_data(pmic, drv, node_name,
0, node, &child);
if (ret) {
debug(" - child binding error: %d\n", ret);
continue;
}
debug(" - bound child device: '%s'\n", child->name);
child->driver_data = trailing_strtol(node_name);
debug(" - set 'child->driver_data': %lu\n",
child->driver_data);
break;
}
if (child)
bind_count++;
else
debug(" - compatible prefix not found\n");
}
static int sandbox_flash_ofdata_to_platdata(struct udevice *dev)
{
struct sandbox_flash_plat *plat = dev_get_platdata(dev);
const void *blob = gd->fdt_blob;
plat->pathname = fdt_getprop(blob, dev_of_offset(dev),
"sandbox,filepath", NULL);
return 0;
}
