static void error_callback(void) { if (adc_context) { adc_context->state = ADC_STATE_ERROR; device_sync_call_complete(&adc_context->sync); } }
static void completed(struct device *dev, int error) { struct spi_dw_config *info = dev->config->config_info; struct spi_dw_data *spi = dev->driver_data; if (error) { goto out; } if (spi->fifo_diff || !((spi->tx_buf && !spi->tx_buf_len && !spi->rx_buf) || (spi->rx_buf && !spi->rx_buf_len && !spi->tx_buf) || (spi->tx_buf && !spi->tx_buf_len && spi->rx_buf && !spi->rx_buf_len))) { return; } out: spi->error = error; /* Disabling interrupts */ write_imr(DW_SPI_IMR_MASK, info->regs); /* Disabling the controller */ clear_bit_ssienr(info->regs); _spi_control_cs(dev, 0); DBG("SPI transaction completed %s error\n", error ? "with" : "without"); device_sync_call_complete(&spi->sync); }
static void pending_transfer_complete(uint32_t id, qm_rc_t rc) { struct pending_transfer *pending = &pending_transfers[id]; struct device *dev = pending->dev; struct spi_qmsi_runtime *context; qm_spi_config_t *cfg; if (!dev) return; context = dev->driver_data; cfg = &context->cfg; pending->counter++; /* * When it is TX/RX transfer this function will be called twice. */ if (cfg->transfer_mode == QM_SPI_TMOD_TX_RX && pending->counter == 1) return; spi_control_cs(dev, false); pending->dev = NULL; pending->counter = 0; context->rc = rc; device_sync_call_complete(&context->sync); }
static inline void _i2c_qse_ss_transfer_complete(struct device *dev) { struct i2c_qse_ss_dev_config * const dw = dev->driver_data; /* Disable and clear all pending interrupts */ _i2c_qse_ss_reg_write(dev, REG_INTR_MASK, IC_INTR_MASK_ALL); _i2c_qse_ss_reg_write(dev, REG_INTR_CLR, IC_INTR_CLR_ALL); device_sync_call_complete(&dw->sync); }
static inline void _i2c_dw_transfer_complete(struct device *dev) { struct i2c_dw_rom_config const * const rom = dev->config->config_info; struct i2c_dw_dev_config * const dw = dev->driver_data; uint32_t value; volatile struct i2c_dw_registers * const regs = (struct i2c_dw_registers *)rom->base_address; regs->ic_intr_mask.raw = DW_DISABLE_ALL_I2C_INT; value = regs->ic_clr_intr; device_sync_call_complete(&dw->sync); }
static void complete_callback(void) { if (adc_context) { device_sync_call_complete(&adc_context->sync); } }
/** * @brief Complete SPI module data transfer operations. * @param dev Pointer to the device structure for the driver instance * @param error Error condition (0 = no error, otherwise an error occurred) * @return None. */ static void spi_k64_complete(struct device *dev, uint32_t error) { struct spi_k64_data *spi_data = dev->driver_data; struct spi_k64_config *info = dev->config->config_info; uint32_t int_config; /* interrupt configuration */ if (error) { DBG("spi_k64_complete - ERROR condition\n"); goto complete; } /* Check for a completed transfer */ if (spi_data->tx_buf && (spi_data->tx_buf_len == 0) && !spi_data->rx_buf) { /* disable Tx interrupts */ int_config = sys_read32(info->regs + SPI_K64_REG_RSER); int_config &= ~SPI_K64_RSER_TFFF_RE; sys_write32(int_config, (info->regs + SPI_K64_REG_RSER)); } else if (spi_data->rx_buf && (spi_data->rx_buf_len == 0) && !spi_data->tx_buf) { /* disable Rx interrupts */ int_config = sys_read32(info->regs + SPI_K64_REG_RSER); int_config &= ~SPI_K64_RSER_RFDF_RE; sys_write32(int_config, (info->regs + SPI_K64_REG_RSER)); } else if (spi_data->tx_buf && spi_data->tx_buf_len == 0 && spi_data->rx_buf && spi_data->rx_buf_len == 0) { /* disable Tx, Rx interrupts */ int_config = sys_read32(info->regs + SPI_K64_REG_RSER); int_config &= ~(SPI_K64_RSER_TFFF_RE | SPI_K64_RSER_RFDF_RE); sys_write32(int_config, (info->regs + SPI_K64_REG_RSER)); } else { return; } complete: spi_data->tx_buf = spi_data->rx_buf = NULL; spi_data->tx_buf_len = spi_data->rx_buf_len = 0; /* Disable transfer operations */ spi_k64_halt(dev); /* Save status */ spi_data->error = error; /* Signal completion */ device_sync_call_complete(&spi_data->sync_info); }