static int display_crc_ctl_parse(struct drm_i915_private *dev_priv, char *buf, size_t len) { #define N_WORDS 3 int n_words; char *words[N_WORDS]; enum pipe pipe; enum intel_pipe_crc_object object; enum intel_pipe_crc_source source; n_words = display_crc_ctl_tokenize(buf, words, N_WORDS); if (n_words != N_WORDS) { DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n", N_WORDS); return -EINVAL; } if (display_crc_ctl_parse_object(words[0], &object) < 0) { DRM_DEBUG_DRIVER("unknown object %s\n", words[0]); return -EINVAL; } if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) { DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]); return -EINVAL; } if (display_crc_ctl_parse_source(words[2], &source) < 0) { DRM_DEBUG_DRIVER("unknown source %s\n", words[2]); return -EINVAL; } return pipe_crc_set_source(dev_priv, pipe, source); }
int intel_crtc_set_crc_source(struct drm_crtc *crtc, const char *source_name, size_t *values_cnt) { struct drm_i915_private *dev_priv = crtc->dev->dev_private; struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[crtc->index]; struct intel_crtc *intel_crtc = to_intel_crtc(crtc); enum intel_display_power_domain power_domain; enum intel_pipe_crc_source source; u32 val = 0; /* shut up gcc */ int ret = 0; if (display_crc_ctl_parse_source(source_name, &source) < 0) { DRM_DEBUG_DRIVER("unknown source %s\n", source_name); return -EINVAL; } power_domain = POWER_DOMAIN_PIPE(crtc->index); if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) { DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n"); return -EIO; } ret = get_new_crc_ctl_reg(dev_priv, crtc->index, &source, &val); if (ret != 0) goto out; if (source) { /* * When IPS gets enabled, the pipe CRC changes. Since IPS gets * enabled and disabled dynamically based on package C states, * user space can't make reliable use of the CRCs, so let's just * completely disable it. */ hsw_disable_ips(intel_crtc); } I915_WRITE(PIPE_CRC_CTL(crtc->index), val); POSTING_READ(PIPE_CRC_CTL(crtc->index)); if (!source) { if (IS_G4X(dev_priv)) g4x_undo_pipe_scramble_reset(dev_priv, crtc->index); else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) vlv_undo_pipe_scramble_reset(dev_priv, crtc->index); else if (IS_HASWELL(dev_priv) && crtc->index == PIPE_A) hsw_trans_edp_pipe_A_crc_wa(dev_priv, false); hsw_enable_ips(intel_crtc); } pipe_crc->skipped = 0; *values_cnt = 5; out: intel_display_power_put(dev_priv, power_domain); return ret; }
int intel_crtc_set_crc_source(struct drm_crtc *crtc, const char *source_name, size_t *values_cnt) { struct drm_i915_private *dev_priv = crtc->dev->dev_private; struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[crtc->index]; enum intel_display_power_domain power_domain; enum intel_pipe_crc_source source; u32 val = 0; /* shut up gcc */ int ret = 0; if (display_crc_ctl_parse_source(source_name, &source) < 0) { DRM_DEBUG_DRIVER("unknown source %s\n", source_name); return -EINVAL; } power_domain = POWER_DOMAIN_PIPE(crtc->index); if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) { DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n"); return -EIO; } ret = get_new_crc_ctl_reg(dev_priv, crtc->index, &source, &val); if (ret != 0) goto out; I915_WRITE(PIPE_CRC_CTL(crtc->index), val); POSTING_READ(PIPE_CRC_CTL(crtc->index)); if (!source) { if (IS_G4X(dev_priv)) g4x_undo_pipe_scramble_reset(dev_priv, crtc->index); else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) vlv_undo_pipe_scramble_reset(dev_priv, crtc->index); else if ((IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) && crtc->index == PIPE_A) hsw_pipe_A_crc_wa(dev_priv, false); } pipe_crc->skipped = 0; *values_cnt = 5; out: intel_display_power_put(dev_priv, power_domain); return ret; }