/* Send a command to the display */ static byte display_send(ins_ctrl_pair icp) { byte status = 0; if (icp[0] & RW) /* Are we reading data? */ { /* Read data from the display */ PORTL &= ~(RS | RW); PORTL |= icp[0]; /* Update the status value with the data returned */ status = PINA; } else { /* Refresh the control lines with new data */ PORTL &= ~(RS | RW); PORTL |= icp[0]; /* Write the data to the data lines */ PORTA = icp[1]; } display_enable(); return status; }
static u08 cmd_display(const u08 *cmd, u08 len) { switch(cmd[1]) { case 'o': // display on display_enable(1); return CMD_OK; case 'f': // display off display_enable(0); return CMD_OK; case 'b': // backlight on display_backlight(1); return CMD_OK; case 'd': // backlight off display_backlight(0); return CMD_OK; default: return CMD_UNKNOWN_ERR; } }
static void display_set_side(byte s) { /* Only apply changes if necessary */ if ((PINL & s) != s) { PORTL &= ~(SIDE1 | SIDE2); PORTL |= s; display_enable(); } }
int display_init(void *lcdbase, int fb_bits_per_pixel, struct display_timing *timing) { struct dc_ctlr *dc_ctlr; const void *blob = gd->fdt_blob; struct udevice *dp_dev; const int href_to_sync = 1, vref_to_sync = 1; int panel_bpp = 18; /* default 18 bits per pixel */ u32 plld_rate; struct gpio_desc vdd_gpio, enable_gpio; int pwm; int node; int ret; ret = uclass_get_device(UCLASS_DISPLAY, 0, &dp_dev); if (ret) return ret; node = fdtdec_next_compatible(blob, 0, COMPAT_NVIDIA_TEGRA124_DC); if (node < 0) return -ENOENT; dc_ctlr = (struct dc_ctlr *)fdtdec_get_addr(blob, node, "reg"); if (fdtdec_decode_display_timing(blob, node, 0, timing)) return -EINVAL; ret = display_update_config_from_edid(dp_dev, &panel_bpp, timing); if (ret) { debug("%s: Failed to decode EDID, using defaults\n", __func__); dump_config(panel_bpp, timing); } if (!get_backlight_info(blob, &vdd_gpio, &enable_gpio, &pwm)) { dm_gpio_set_value(&vdd_gpio, 1); debug("%s: backlight vdd setting gpio %08x to %d\n", __func__, gpio_get_number(&vdd_gpio), 1); } /* * The plld is programmed with the assumption of the SHIFT_CLK_DIVIDER * and PIXEL_CLK_DIVIDER are zero (divide by 1). See the * update_display_mode() for detail. */ plld_rate = clock_set_display_rate(timing->pixelclock.typ * 2); if (plld_rate == 0) { printf("dc: clock init failed\n"); return -EIO; } else if (plld_rate != timing->pixelclock.typ * 2) { debug("dc: plld rounded to %u\n", plld_rate); timing->pixelclock.typ = plld_rate / 2; } /* Init dc */ ret = tegra_dc_init(dc_ctlr); if (ret) { debug("dc: init failed\n"); return ret; } /* Configure dc mode */ ret = update_display_mode(dc_ctlr, timing, href_to_sync, vref_to_sync); if (ret) { debug("dc: failed to configure display mode\n"); return ret; } /* Enable dp */ ret = display_enable(dp_dev, panel_bpp, timing); if (ret) return ret; ret = update_window(dc_ctlr, (ulong)lcdbase, fb_bits_per_pixel, timing); if (ret) return ret; /* Set up Tegra PWM to drive the panel backlight */ pwm_enable(pwm, 0, 220, 0x2e); udelay(10 * 1000); if (dm_gpio_is_valid(&enable_gpio)) { dm_gpio_set_value(&enable_gpio, 1); debug("%s: backlight enable setting gpio %08x to %d\n", __func__, gpio_get_number(&enable_gpio), 1); } return 0; }
/** * rk_display_init() - Try to enable the given display device * * This function performs many steps: * - Finds the display device being referenced by @ep_node * - Puts the VOP's ID into its uclass platform data * - Probes the device to set it up * - Reads the EDID timing information * - Sets up the VOP clocks, etc. for the selected pixel clock and display mode * - Enables the display (the display device handles this and will do different * things depending on the display type) * - Tells the uclass about the display resolution so that the console will * appear correctly * * @dev: VOP device that we want to connect to the display * @fbbase: Frame buffer address * @l2bpp Log2 of bits-per-pixels for the display * @ep_node: Device tree node to process - this is the offset of an endpoint * node within the VOP's 'port' list. * @return 0 if OK, -ve if something went wrong */ int rk_display_init(struct udevice *dev, ulong fbbase, enum video_log2_bpp l2bpp, int ep_node) { struct video_priv *uc_priv = dev_get_uclass_priv(dev); const void *blob = gd->fdt_blob; struct rk_vop_priv *priv = dev_get_priv(dev); int vop_id, remote_vop_id; struct rk3288_vop *regs = priv->regs; struct display_timing timing; struct udevice *disp; int ret, remote, i, offset; struct display_plat *disp_uc_plat; struct udevice *clk; vop_id = fdtdec_get_int(blob, ep_node, "reg", -1); debug("vop_id=%d\n", vop_id); remote = fdtdec_lookup_phandle(blob, ep_node, "remote-endpoint"); if (remote < 0) return -EINVAL; remote_vop_id = fdtdec_get_int(blob, remote, "reg", -1); debug("remote vop_id=%d\n", remote_vop_id); for (i = 0, offset = remote; i < 3 && offset > 0; i++) offset = fdt_parent_offset(blob, offset); if (offset < 0) { debug("%s: Invalid remote-endpoint position\n", dev->name); return -EINVAL; } ret = uclass_find_device_by_of_offset(UCLASS_DISPLAY, offset, &disp); if (ret) { debug("%s: device '%s' display not found (ret=%d)\n", __func__, dev->name, ret); return ret; } disp_uc_plat = dev_get_uclass_platdata(disp); debug("Found device '%s', disp_uc_priv=%p\n", disp->name, disp_uc_plat); disp_uc_plat->source_id = remote_vop_id; disp_uc_plat->src_dev = dev; ret = device_probe(disp); if (ret) { debug("%s: device '%s' display won't probe (ret=%d)\n", __func__, dev->name, ret); return ret; } ret = display_read_timing(disp, &timing); if (ret) { debug("%s: Failed to read timings\n", __func__); return ret; } ret = rkclk_get_clk(CLK_NEW, &clk); if (!ret) { ret = clk_set_periph_rate(clk, DCLK_VOP0 + remote_vop_id, timing.pixelclock.typ); } if (ret) { debug("%s: Failed to set pixel clock: ret=%d\n", __func__, ret); return ret; } rkvop_mode_set(regs, &timing, vop_id); rkvop_enable(regs, fbbase, 1 << l2bpp, &timing); ret = display_enable(disp, 1 << l2bpp, &timing); if (ret) return ret; uc_priv->xsize = timing.hactive.typ; uc_priv->ysize = timing.vactive.typ; uc_priv->bpix = l2bpp; debug("fb=%lx, size=%d %d\n", fbbase, uc_priv->xsize, uc_priv->ysize); return 0; }
static int display_init(struct udevice *dev, void *lcdbase, int fb_bits_per_pixel, struct display_timing *timing) { struct display_plat *disp_uc_plat; struct dc_ctlr *dc_ctlr; struct udevice *dp_dev; const int href_to_sync = 1, vref_to_sync = 1; int panel_bpp = 18; /* default 18 bits per pixel */ u32 plld_rate; int ret; /* * Before we probe the display device (eDP), tell it that this device * is the source of the display data. */ ret = uclass_find_first_device(UCLASS_DISPLAY, &dp_dev); if (ret) { debug("%s: device '%s' display not found (ret=%d)\n", __func__, dev->name, ret); return ret; } disp_uc_plat = dev_get_uclass_platdata(dp_dev); debug("Found device '%s', disp_uc_priv=%p\n", dp_dev->name, disp_uc_plat); disp_uc_plat->src_dev = dev; ret = uclass_get_device(UCLASS_DISPLAY, 0, &dp_dev); if (ret) { debug("%s: Failed to probe eDP, ret=%d\n", __func__, ret); return ret; } dc_ctlr = (struct dc_ctlr *)dev_read_addr(dev); if (ofnode_decode_display_timing(dev_ofnode(dev), 0, timing)) { debug("%s: Failed to decode display timing\n", __func__); return -EINVAL; } ret = display_update_config_from_edid(dp_dev, &panel_bpp, timing); if (ret) { debug("%s: Failed to decode EDID, using defaults\n", __func__); dump_config(panel_bpp, timing); } /* * The plld is programmed with the assumption of the SHIFT_CLK_DIVIDER * and PIXEL_CLK_DIVIDER are zero (divide by 1). See the * update_display_mode() for detail. */ plld_rate = clock_set_display_rate(timing->pixelclock.typ * 2); if (plld_rate == 0) { printf("dc: clock init failed\n"); return -EIO; } else if (plld_rate != timing->pixelclock.typ * 2) { debug("dc: plld rounded to %u\n", plld_rate); timing->pixelclock.typ = plld_rate / 2; } /* Init dc */ ret = tegra_dc_init(dc_ctlr); if (ret) { debug("dc: init failed\n"); return ret; } /* Configure dc mode */ ret = update_display_mode(dc_ctlr, timing, href_to_sync, vref_to_sync); if (ret) { debug("dc: failed to configure display mode\n"); return ret; } /* Enable dp */ ret = display_enable(dp_dev, panel_bpp, timing); if (ret) { debug("dc: failed to enable display: ret=%d\n", ret); return ret; } ret = update_window(dc_ctlr, (ulong)lcdbase, fb_bits_per_pixel, timing); if (ret) { debug("dc: failed to update window\n"); return ret; } debug("%s: ready\n", __func__); return 0; }
void display_init(void) { display_enable(true); }