/* Test that we can use the swapcase device correctly */ static int dm_test_pci_swapcase(struct unit_test_state *uts) { struct udevice *emul, *swap; ulong io_addr, mem_addr; char *ptr; /* Check that asking for the device automatically fires up PCI */ ut_assertok(uclass_get_device(UCLASS_PCI_EMUL, 0, &emul)); ut_assertok(dm_pci_bus_find_bdf(PCI_BDF(0, 0x1f, 0), &swap)); ut_assert(device_active(swap)); /* First test I/O */ io_addr = dm_pci_read_bar32(swap, 0); outb(2, io_addr); ut_asserteq(2, inb(io_addr)); /* * Now test memory mapping - note we must unmap and remap to cause * the swapcase emulation to see our data and response. */ mem_addr = dm_pci_read_bar32(swap, 1); ptr = map_sysmem(mem_addr, 20); strcpy(ptr, "This is a TesT"); unmap_sysmem(ptr); ptr = map_sysmem(mem_addr, 20); ut_asserteq_str("tHIS IS A tESt", ptr); unmap_sysmem(ptr); return 0; }
int fdtdec_get_pci_bar32(struct udevice *dev, struct fdt_pci_addr *addr, u32 *bar) { int barnum; /* extract the bar number from fdt_pci_addr */ barnum = addr->phys_hi & 0xff; if ((barnum < PCI_BASE_ADDRESS_0) || (barnum > PCI_CARDBUS_CIS)) return -EINVAL; barnum = (barnum - PCI_BASE_ADDRESS_0) / 4; *bar = dm_pci_read_bar32(dev, barnum); return 0; }
static void bd82x6x_sata_init(struct udevice *dev, struct udevice *pch) { unsigned int port_map, speed_support, port_tx; const void *blob = gd->fdt_blob; int node = dev->of_offset; const char *mode; u32 reg32; u16 reg16; debug("SATA: Initializing...\n"); /* SATA configuration */ port_map = fdtdec_get_int(blob, node, "intel,sata-port-map", 0); speed_support = fdtdec_get_int(blob, node, "sata_interface_speed_support", 0); mode = fdt_getprop(blob, node, "intel,sata-mode", NULL); if (!mode || !strcmp(mode, "ahci")) { u32 abar; debug("SATA: Controller in AHCI mode\n"); /* Set timings */ dm_pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS | IDE_PPE0 | IDE_IE0 | IDE_TIME0); dm_pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS); /* Sync DMA */ dm_pci_write_config16(dev, IDE_SDMA_CNT, IDE_PSDE0); dm_pci_write_config16(dev, IDE_SDMA_TIM, 0x0001); common_sata_init(dev, 0x8000 | port_map); /* Initialize AHCI memory-mapped space */ abar = dm_pci_read_bar32(dev, 5); debug("ABAR: %08X\n", abar); /* CAP (HBA Capabilities) : enable power management */ reg32 = readl(abar + 0x00); reg32 |= 0x0c006000; /* set PSC+SSC+SALP+SSS */ reg32 &= ~0x00020060; /* clear SXS+EMS+PMS */ /* Set ISS, if available */ if (speed_support) { reg32 &= ~0x00f00000; reg32 |= (speed_support & 0x03) << 20; } writel(reg32, abar + 0x00); /* PI (Ports implemented) */ writel(port_map, abar + 0x0c); (void) readl(abar + 0x0c); /* Read back 1 */ (void) readl(abar + 0x0c); /* Read back 2 */ /* CAP2 (HBA Capabilities Extended)*/ reg32 = readl(abar + 0x24); reg32 &= ~0x00000002; writel(reg32, abar + 0x24); /* VSP (Vendor Specific Register */ reg32 = readl(abar + 0xa0); reg32 &= ~0x00000005; writel(reg32, abar + 0xa0); } else if (!strcmp(mode, "combined")) { debug("SATA: Controller in combined mode\n"); /* No AHCI: clear AHCI base */ dm_pci_write_bar32(dev, 5, 0x00000000); /* And without AHCI BAR no memory decoding */ dm_pci_read_config16(dev, PCI_COMMAND, ®16); reg16 &= ~PCI_COMMAND_MEMORY; dm_pci_write_config16(dev, PCI_COMMAND, reg16); dm_pci_write_config8(dev, 0x09, 0x80); /* Set timings */ dm_pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS); dm_pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS | IDE_PPE0 | IDE_IE0 | IDE_TIME0); /* Sync DMA */ dm_pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0); dm_pci_write_config16(dev, IDE_SDMA_TIM, 0x0200); common_sata_init(dev, port_map); } else { debug("SATA: Controller in plain-ide mode\n"); /* No AHCI: clear AHCI base */ dm_pci_write_bar32(dev, 5, 0x00000000); /* And without AHCI BAR no memory decoding */ dm_pci_read_config16(dev, PCI_COMMAND, ®16); reg16 &= ~PCI_COMMAND_MEMORY; dm_pci_write_config16(dev, PCI_COMMAND, reg16); /* * Native mode capable on both primary and secondary (0xa) * OR'ed with enabled (0x50) = 0xf */ dm_pci_write_config8(dev, 0x09, 0x8f); /* Set timings */ dm_pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS | IDE_PPE0 | IDE_IE0 | IDE_TIME0); dm_pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | IDE_SITRE | IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS | IDE_IE0 | IDE_TIME0); /* Sync DMA */ dm_pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0 | IDE_PSDE0); dm_pci_write_config16(dev, IDE_SDMA_TIM, 0x0201); common_sata_init(dev, port_map); } /* Set Gen3 Transmitter settings if needed */ port_tx = fdtdec_get_int(blob, node, "intel,sata-port0-gen3-tx", 0); if (port_tx) pch_iobp_update(pch, SATA_IOBP_SP0G3IR, 0, port_tx); port_tx = fdtdec_get_int(blob, node, "intel,sata-port1-gen3-tx", 0); if (port_tx) pch_iobp_update(pch, SATA_IOBP_SP1G3IR, 0, port_tx); /* Additional Programming Requirements */ sir_write(dev, 0x04, 0x00001600); sir_write(dev, 0x28, 0xa0000033); reg32 = sir_read(dev, 0x54); reg32 &= 0xff000000; reg32 |= 0x5555aa; sir_write(dev, 0x54, reg32); sir_write(dev, 0x64, 0xcccc8484); reg32 = sir_read(dev, 0x68); reg32 &= 0xffff0000; reg32 |= 0xcccc; sir_write(dev, 0x68, reg32); reg32 = sir_read(dev, 0x78); reg32 &= 0x0000ffff; reg32 |= 0x88880000; sir_write(dev, 0x78, reg32); sir_write(dev, 0x84, 0x001c7000); sir_write(dev, 0x88, 0x88338822); sir_write(dev, 0xa0, 0x001c7000); sir_write(dev, 0xc4, 0x0c0c0c0c); sir_write(dev, 0xc8, 0x0c0c0c0c); sir_write(dev, 0xd4, 0x10000000); pch_iobp_update(pch, 0xea004001, 0x3fffffff, 0xc0000000); pch_iobp_update(pch, 0xea00408a, 0xfffffcff, 0x00000100); }