void sCPU::dma_transfer(bool direction, uint8 bbus, uint32 abus) {
if(direction == 0) {
//a->b transfer (to $21xx)
if(bbus == 0x80 && ((abus & 0xfe0000) == 0x7e0000 || (abus & 0x40e000) == 0x0000)) {
//illegal WRAM->WRAM transfer (bus conflict)
//read most likely occurs; no write occurs
//read is irrelevent, as it cannot be observed by software
dma_add_clocks(8);
} else {
dma_add_clocks(4);
uint8 data = dma_read(abus);
dma_add_clocks(4);
bus.write(0x2100 | bbus, data);
}
} else {
//b->a transfer (from $21xx)
if(bbus == 0x80 && ((abus & 0xfe0000) == 0x7e0000 || (abus & 0x40e000) == 0x0000)) {
//illegal WRAM->WRAM transfer (bus conflict)
//no read occurs; write does occur
dma_add_clocks(8);
bus.write(abus, 0x00); //does not write S-CPU MDR
} else {
dma_add_clocks(4);
uint8 data = bus.read(0x2100 | bbus);
dma_add_clocks(4);
if(dma_addr_valid(abus) == true) {
bus.write(abus, data);
}
}
}
cycle_edge();
}
void CPU::dma_transfer(bool direction, uint8 bbus, uint32 abus) {
if(direction == 0) {
add_clocks(4);
regs.mdr = dma_read(abus);
add_clocks(4);
if (dma_transfer_valid(bbus, abus)) bus.write(0x2100 | bbus, regs.mdr);
} else {
add_clocks(4);
regs.mdr = dma_transfer_valid(bbus, abus) ? bus.read(0x2100 | bbus) : 0x00;
add_clocks(4);
if (dma_addr_valid(abus)) bus.write(abus, regs.mdr);
}
}
uint8 CPU::dma_read(uint32 abus) {
if(dma_addr_valid(abus) == false) return 0x00;
return bus.read(abus);
}
uint8 sCPU::dma_read(uint32 abus) {
if(dma_addr_valid(abus) == false) return 0x00; //does not return S-CPU MDR
return bus.read(abus);
}
