/* Must be called with the arena lock held */ static long iommu_arena_find_pages(struct device *dev, struct pci_iommu_arena *arena, long n, long mask) { unsigned long *ptes; long i, p, nent; int pass = 0; unsigned long base; unsigned long boundary_size; base = arena->dma_base >> PAGE_SHIFT; if (dev) { boundary_size = dma_get_seg_boundary(dev) + 1; boundary_size >>= PAGE_SHIFT; } else {
static unsigned long iommu_range_alloc(struct device *dev, struct iommu_table *tbl, unsigned long npages, unsigned long *handle, unsigned long mask, unsigned int align_order) { unsigned long n, end, start; unsigned long limit; int largealloc = npages > 15; int pass = 0; unsigned long align_mask; unsigned long boundary_size; unsigned long flags; unsigned int pool_nr; struct iommu_pool *pool; align_mask = 0xffffffffffffffffl >> (64 - align_order); /* This allocator was derived from x86_64's bit string search */ /* Sanity check */ if (unlikely(npages == 0)) { if (printk_ratelimit()) WARN_ON(1); return DMA_ERROR_CODE; } if (should_fail_iommu(dev)) return DMA_ERROR_CODE; /* * We don't need to disable preemption here because any CPU can * safely use any IOMMU pool. */ pool_nr = __raw_get_cpu_var(iommu_pool_hash) & (tbl->nr_pools - 1); if (largealloc) pool = &(tbl->large_pool); else pool = &(tbl->pools[pool_nr]); spin_lock_irqsave(&(pool->lock), flags); again: if ((pass == 0) && handle && *handle && (*handle >= pool->start) && (*handle < pool->end)) start = *handle; else start = pool->hint; limit = pool->end; /* The case below can happen if we have a small segment appended * to a large, or when the previous alloc was at the very end of * the available space. If so, go back to the initial start. */ if (start >= limit) start = pool->start; if (limit + tbl->it_offset > mask) { limit = mask - tbl->it_offset + 1; /* If we're constrained on address range, first try * at the masked hint to avoid O(n) search complexity, * but on second pass, start at 0 in pool 0. */ if ((start & mask) >= limit || pass > 0) { spin_unlock(&(pool->lock)); pool = &(tbl->pools[0]); spin_lock(&(pool->lock)); start = pool->start; } else { start &= mask; } } if (dev) boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1, 1 << tbl->it_page_shift); else boundary_size = ALIGN(1UL << 32, 1 << tbl->it_page_shift); /* 4GB boundary for iseries_hv_alloc and iseries_hv_map */ n = iommu_area_alloc(tbl->it_map, limit, start, npages, tbl->it_offset, boundary_size >> tbl->it_page_shift, align_mask); if (n == -1) { if (likely(pass == 0)) { /* First try the pool from the start */ pool->hint = pool->start; pass++; goto again; } else if (pass <= tbl->nr_pools) { /* Now try scanning all the other pools */ spin_unlock(&(pool->lock)); pool_nr = (pool_nr + 1) & (tbl->nr_pools - 1); pool = &tbl->pools[pool_nr]; spin_lock(&(pool->lock)); pool->hint = pool->start; pass++; goto again; } else { /* Give up */ spin_unlock_irqrestore(&(pool->lock), flags); return DMA_ERROR_CODE; } } end = n + npages; /* Bump the hint to a new block for small allocs. */ if (largealloc) { /* Don't bump to new block to avoid fragmentation */ pool->hint = end; } else { /* Overflow will be taken care of at the next allocation */ pool->hint = (end + tbl->it_blocksize - 1) & ~(tbl->it_blocksize - 1); } /* Update handle for SG allocations */ if (handle) *handle = end; spin_unlock_irqrestore(&(pool->lock), flags); return n; }
static unsigned long iommu_range_alloc(struct device *dev, struct iommu_table *tbl, unsigned long npages, unsigned long *handle, unsigned long mask, unsigned int align_order) { unsigned long n, end, start; unsigned long limit; int largealloc = npages > 15; int pass = 0; unsigned long align_mask; unsigned long boundary_size; align_mask = 0xffffffffffffffffl >> (64 - align_order); /* This allocator was derived from x86_64's bit string search */ /* Sanity check */ if (unlikely(npages == 0)) { if (printk_ratelimit()) WARN_ON(1); return DMA_ERROR_CODE; } if (handle && *handle) start = *handle; else start = largealloc ? tbl->it_largehint : tbl->it_hint; /* Use only half of the table for small allocs (15 pages or less) */ limit = largealloc ? tbl->it_size : tbl->it_halfpoint; if (largealloc && start < tbl->it_halfpoint) start = tbl->it_halfpoint; /* The case below can happen if we have a small segment appended * to a large, or when the previous alloc was at the very end of * the available space. If so, go back to the initial start. */ if (start >= limit) start = largealloc ? tbl->it_largehint : tbl->it_hint; again: if (limit + tbl->it_offset > mask) { limit = mask - tbl->it_offset + 1; /* If we're constrained on address range, first try * at the masked hint to avoid O(n) search complexity, * but on second pass, start at 0. */ if ((start & mask) >= limit || pass > 0) start = 0; else start &= mask; } if (dev) boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1, 1 << IOMMU_PAGE_SHIFT); else boundary_size = ALIGN(1UL << 32, 1 << IOMMU_PAGE_SHIFT); /* 4GB boundary for iseries_hv_alloc and iseries_hv_map */ n = iommu_area_alloc(tbl->it_map, limit, start, npages, tbl->it_offset, boundary_size >> IOMMU_PAGE_SHIFT, align_mask); if (n == -1) { if (likely(pass < 2)) { /* First failure, just rescan the half of the table. * Second failure, rescan the other half of the table. */ start = (largealloc ^ pass) ? tbl->it_halfpoint : 0; limit = pass ? tbl->it_size : limit; pass++; goto again; } else { /* Third failure, give up */ return DMA_ERROR_CODE; } } end = n + npages; /* Bump the hint to a new block for small allocs. */ if (largealloc) { /* Don't bump to new block to avoid fragmentation */ tbl->it_largehint = end; } else { /* Overflow will be taken care of at the next allocation */ tbl->it_hint = (end + tbl->it_blocksize - 1) & ~(tbl->it_blocksize - 1); } /* Update handle for SG allocations */ if (handle) *handle = end; return n; }
unsigned long iommu_tbl_range_alloc(struct device *dev, struct iommu_map_table *iommu, unsigned long npages, unsigned long *handle, unsigned long mask, unsigned int align_order) { unsigned int pool_hash = __this_cpu_read(iommu_hash_common); unsigned long n, end, start, limit, boundary_size; struct iommu_pool *pool; int pass = 0; unsigned int pool_nr; unsigned int npools = iommu->nr_pools; unsigned long flags; bool large_pool = ((iommu->flags & IOMMU_HAS_LARGE_POOL) != 0); bool largealloc = (large_pool && npages > iommu_large_alloc); unsigned long shift; unsigned long align_mask = 0; if (align_order > 0) align_mask = 0xffffffffffffffffl >> (64 - align_order); /* Sanity check */ if (unlikely(npages == 0)) { WARN_ON_ONCE(1); return DMA_ERROR_CODE; } if (largealloc) { pool = &(iommu->large_pool); pool_nr = 0; /* to keep compiler happy */ } else { /* pick out pool_nr */ pool_nr = pool_hash & (npools - 1); pool = &(iommu->pools[pool_nr]); } spin_lock_irqsave(&pool->lock, flags); again: if (pass == 0 && handle && *handle && (*handle >= pool->start) && (*handle < pool->end)) start = *handle; else start = pool->hint; limit = pool->end; /* The case below can happen if we have a small segment appended * to a large, or when the previous alloc was at the very end of * the available space. If so, go back to the beginning. If a * flush is needed, it will get done based on the return value * from iommu_area_alloc() below. */ if (start >= limit) start = pool->start; shift = iommu->table_map_base >> iommu->table_shift; if (limit + shift > mask) { limit = mask - shift + 1; /* If we're constrained on address range, first try * at the masked hint to avoid O(n) search complexity, * but on second pass, start at 0 in pool 0. */ if ((start & mask) >= limit || pass > 0) { spin_unlock(&(pool->lock)); pool = &(iommu->pools[0]); spin_lock(&(pool->lock)); start = pool->start; } else { start &= mask; } } if (dev) boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1, 1 << iommu->table_shift); else boundary_size = ALIGN(1ULL << 32, 1 << iommu->table_shift); boundary_size = boundary_size >> iommu->table_shift; /* * if the skip_span_boundary_check had been set during init, we set * things up so that iommu_is_span_boundary() merely checks if the * (index + npages) < num_tsb_entries */ if ((iommu->flags & IOMMU_NO_SPAN_BOUND) != 0) { shift = 0; boundary_size = iommu->poolsize * iommu->nr_pools; } n = iommu_area_alloc(iommu->map, limit, start, npages, shift, boundary_size, align_mask); if (n == -1) { if (likely(pass == 0)) { /* First failure, rescan from the beginning. */ pool->hint = pool->start; set_flush(iommu); pass++; goto again; } else if (!largealloc && pass <= iommu->nr_pools) { spin_unlock(&(pool->lock)); pool_nr = (pool_nr + 1) & (iommu->nr_pools - 1); pool = &(iommu->pools[pool_nr]); spin_lock(&(pool->lock)); pool->hint = pool->start; set_flush(iommu); pass++; goto again; } else { /* give up */ n = DMA_ERROR_CODE; goto bail; } } if (iommu->lazy_flush && (n < pool->hint || need_flush(iommu))) { clear_flush(iommu); iommu->lazy_flush(iommu); } end = n + npages; pool->hint = end; /* Update handle for SG allocations */ if (handle) *handle = end; bail: spin_unlock_irqrestore(&(pool->lock), flags); return n; }