static int pci_piix3_xen_ide_unplug(DeviceState *dev) { PCIDevice *pci_dev; PCIIDEState *pci_ide; DriveInfo *di; int i = 0; pci_dev = DO_UPCAST(PCIDevice, qdev, dev); pci_ide = DO_UPCAST(PCIIDEState, dev, pci_dev); for (; i < 3; i++) { di = drive_get_by_index(IF_IDE, i); if (di != NULL && !di->media_cd) { DeviceState *ds = bdrv_get_attached_dev(di->bdrv); if (ds) { bdrv_detach_dev(di->bdrv, ds); } bdrv_close(di->bdrv); pci_ide->bus[di->bus].ifs[di->unit].bs = NULL; drive_put_ref(di); } } qdev_reset_all(&(pci_ide->dev.qdev)); return 0; }
int pci_piix3_xen_ide_unplug(DeviceState *dev) { PCIIDEState *pci_ide; DriveInfo *di; int i; IDEDevice *idedev; pci_ide = PCI_IDE(dev); for (i = 0; i < 4; i++) { di = drive_get_by_index(IF_IDE, i); if (di != NULL && !di->media_cd) { BlockBackend *blk = blk_by_legacy_dinfo(di); DeviceState *ds = blk_get_attached_dev(blk); if (ds) { blk_detach_dev(blk, ds); } pci_ide->bus[di->bus].ifs[di->unit].blk = NULL; if (!(i % 2)) { idedev = pci_ide->bus[di->bus].master; } else { idedev = pci_ide->bus[di->bus].slave; } idedev->conf.blk = NULL; monitor_remove_blk(blk); blk_unref(blk); } } qdev_reset_all(DEVICE(dev)); return 0; }
static void ronaldo_sdhci_realize(DeviceState *dev, Error **errp) { DeviceClass *dc_parent = DEVICE_CLASS(RONALDO_SDHCI_PARENT_CLASS); RonaldoSDHCIState *s = RONALDO_SDHCI(dev); DriveInfo *di_sd; DriveInfo *di_mmc; di_sd = drive_get_by_index(IF_SD , s->drive_index); di_mmc = drive_get_by_index(IF_SD, (s->drive_index + 2)); s->sd_card = sd_init(di_sd ? blk_by_legacy_dinfo(di_sd) : NULL, false); s->mmc_card = mmc_init(di_mmc ? blk_by_legacy_dinfo(di_mmc) : NULL); dc_parent->realize(dev, errp); qdev_init_gpio_in_named(dev, ronaldo_sdhci_slottype_handler, "SLOTTYPE", 1); }
int pci_piix3_xen_ide_unplug(DeviceState *dev) { PCIIDEState *pci_ide; DriveInfo *di; int i = 0; pci_ide = PCI_IDE(dev); for (; i < 3; i++) { di = drive_get_by_index(IF_IDE, i); if (di != NULL && !di->media_cd) { DeviceState *ds = bdrv_get_attached_dev(di->bdrv); if (ds) { bdrv_detach_dev(di->bdrv, ds); } bdrv_close(di->bdrv); pci_ide->bus[di->bus].ifs[di->unit].bs = NULL; drive_del(di); } } qdev_reset_all(DEVICE(dev)); return 0; }
static void riscv_board_init(QEMUMachineInitArgs *args) { ram_addr_t ram_size = args->ram_size; const char *cpu_model = args->cpu_model; const char *kernel_filename = args->kernel_filename; const char *kernel_cmdline = args->kernel_cmdline; const char *initrd_filename = args->initrd_filename; MemoryRegion *system_memory = get_system_memory(); MemoryRegion *main_mem = g_new(MemoryRegion, 1); RISCVCPU *cpu; CPURISCVState *env; int i; #ifdef CONFIG_RISCV_HTIF DriveInfo *htifbd_drive; char *htifbd_fname; // htif block device filename #endif DeviceState *dev = qdev_create(NULL, TYPE_RISCV_BOARD); object_property_set_bool(OBJECT(dev), true, "realized", NULL); /* Make sure the first 3 serial ports are associated with a device. */ for(i = 0; i < 3; i++) { if (!serial_hds[i]) { char label[32]; snprintf(label, sizeof(label), "serial%d", i); serial_hds[i] = qemu_chr_new(label, "null", NULL); } } /* init CPUs */ if (cpu_model == NULL) { cpu_model = "riscv-generic"; } for (i = 0; i < smp_cpus; i++) { cpu = cpu_riscv_init(cpu_model); if (cpu == NULL) { fprintf(stderr, "Unable to find CPU definition\n"); exit(1); } env = &cpu->env; /* Init internal devices */ cpu_riscv_irq_init_cpu(env); cpu_riscv_clock_init(env); qemu_register_reset(main_cpu_reset, cpu); } cpu = RISCV_CPU(first_cpu); env = &cpu->env; /* register system main memory (actual RAM) */ memory_region_init_ram(main_mem, NULL, "riscv_board.ram", ram_size); vmstate_register_ram_global(main_mem); memory_region_add_subregion(system_memory, 0x0, main_mem); if (kernel_filename) { /* Write a small bootloader to the flash location. */ loaderparams.ram_size = ram_size; loaderparams.kernel_filename = kernel_filename; loaderparams.kernel_cmdline = kernel_cmdline; loaderparams.initrd_filename = initrd_filename; load_kernel(); } // write memory amount in MiB to 0x0 stl_p(memory_region_get_ram_ptr(main_mem), loaderparams.ram_size >> 20); #ifdef CONFIG_RISCV_HTIF serial_mm_init(system_memory, 0x3f8, 0, env->irq[4], 1843200/16, serial_hds[0], DEVICE_NATIVE_ENDIAN); // setup HTIF Block Device if one is specified as -hda FILENAME htifbd_drive = drive_get_by_index(IF_IDE, 0); if (NULL == htifbd_drive) { htifbd_fname = NULL; } else { htifbd_fname = (*(htifbd_drive->bdrv)).filename; } // add htif device 0x400 - 0x410 htif_mm_init(system_memory, 0x400, env->irq[0], main_mem, htifbd_fname); #else // add serial device 0x3f8-0x3ff serial_mm_init(system_memory, 0x3f8, 0, env->irq[1], 1843200/16, serial_hds[0], DEVICE_NATIVE_ENDIAN); /* Create MMIO transports, to which virtio backends created by the * user are automatically connected as needed. If no backend is * present, the transport simply remains harmlessly idle. * Each memory-mapped region is 0x200 bytes in size. */ sysbus_create_simple("virtio-mmio", 0x400, env->irq[2]); sysbus_create_simple("virtio-mmio", 0x600, env->irq[3]); sysbus_create_simple("virtio-mmio", 0x800, env->irq[4]); #endif /* Init internal devices */ cpu_riscv_irq_init_cpu(env); cpu_riscv_clock_init(env); }