static int nouveau_init_card_mappings(struct drm_device *dev)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
int ret;
/* resource 0 is mmio regs */
/* resource 1 is linear FB */
/* resource 2 is RAMIN (mmio regs + 0x1000000) */
/* resource 6 is bios */
/* map the mmio regs */
ret = drm_addmap(dev, drm_get_resource_start(dev, 0),
drm_get_resource_len(dev, 0),
_DRM_REGISTERS, _DRM_READ_ONLY, &dev_priv->mmio);
if (ret) {
DRM_ERROR("Unable to initialize the mmio mapping (%d). "
"Please report your setup to " DRIVER_EMAIL "\n",
ret);
return -EINVAL;
}
DRM_DEBUG("regs mapped ok at 0x%lx\n", dev_priv->mmio->offset);
/* map larger RAMIN aperture on NV40 cards */
dev_priv->ramin = NULL;
if (dev_priv->card_type >= NV_40) {
int ramin_resource = 2;
if (drm_get_resource_len(dev, ramin_resource) == 0)
ramin_resource = 3;
ret = drm_addmap(dev,
drm_get_resource_start(dev, ramin_resource),
drm_get_resource_len(dev, ramin_resource),
_DRM_REGISTERS, _DRM_READ_ONLY,
&dev_priv->ramin);
if (ret) {
DRM_ERROR("Failed to init RAMIN mapping, "
"limited instance memory available\n");
dev_priv->ramin = NULL;
}
}
/* On older cards (or if the above failed), create a map covering
* the BAR0 PRAMIN aperture */
if (!dev_priv->ramin) {
ret = drm_addmap(dev,
drm_get_resource_start(dev, 0) + NV_RAMIN,
(1*1024*1024),
_DRM_REGISTERS, _DRM_READ_ONLY,
&dev_priv->ramin);
if (ret) {
DRM_ERROR("Failed to map BAR0 PRAMIN: %d\n", ret);
return ret;
}
}
return 0;
}
static int drm_setup(struct drm_device *dev)
{
drm_local_map_t *map;
int i;
DRM_LOCK_ASSERT(dev);
/* prebuild the SAREA */
i = drm_addmap(dev, 0, SAREA_MAX, _DRM_SHM,
_DRM_CONTAINS_LOCK, &map);
if (i != 0)
return i;
if (dev->driver->firstopen)
dev->driver->firstopen(dev);
dev->buf_use = 0;
if (drm_core_check_feature(dev, DRIVER_HAVE_DMA)) {
i = drm_dma_setup(dev);
if (i != 0)
return i;
}
for (i = 0; i < DRM_HASH_SIZE; i++) {
dev->magiclist[i].head = NULL;
dev->magiclist[i].tail = NULL;
}
init_waitqueue_head(&dev->lock.lock_queue);
if (!drm_core_check_feature(dev, DRIVER_MODESET))
dev->irq_enabled = 0;
dev->context_flag = 0;
dev->last_context = 0;
dev->if_version = 0;
dev->buf_sigio = NULL;
DRM_DEBUG("\n");
return 0;
}
/*
* Initialize mappings. On Savage4 and SavageIX the alignment
* and size of the aperture is not suitable for automatic MTRR setup
* in drm_addmap. Therefore we add them manually before the maps are
* initialized, and tear them down on last close.
*/
int savage_driver_firstopen(struct drm_device *dev)
{
drm_savage_private_t *dev_priv = dev->dev_private;
unsigned long mmio_base, fb_base, fb_size, aperture_base;
/* fb_rsrc and aper_rsrc aren't really used currently, but still exist
* in case we decide we need information on the BAR for BSD in the
* future.
*/
unsigned int fb_rsrc, aper_rsrc;
int ret = 0;
dev_priv->mtrr[0].handle = -1;
dev_priv->mtrr[1].handle = -1;
dev_priv->mtrr[2].handle = -1;
if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) {
fb_rsrc = 0;
fb_base = pci_resource_start(dev->pdev, 0);
fb_size = SAVAGE_FB_SIZE_S3;
mmio_base = fb_base + SAVAGE_FB_SIZE_S3;
aper_rsrc = 0;
aperture_base = fb_base + SAVAGE_APERTURE_OFFSET;
/* this should always be true */
if (pci_resource_len(dev->pdev, 0) == 0x08000000) {
/* Don't make MMIO write-cobining! We need 3
* MTRRs. */
dev_priv->mtrr[0].base = fb_base;
dev_priv->mtrr[0].size = 0x01000000;
dev_priv->mtrr[0].handle =
drm_mtrr_add(dev_priv->mtrr[0].base,
dev_priv->mtrr[0].size, DRM_MTRR_WC);
dev_priv->mtrr[1].base = fb_base + 0x02000000;
dev_priv->mtrr[1].size = 0x02000000;
dev_priv->mtrr[1].handle =
drm_mtrr_add(dev_priv->mtrr[1].base,
dev_priv->mtrr[1].size, DRM_MTRR_WC);
dev_priv->mtrr[2].base = fb_base + 0x04000000;
dev_priv->mtrr[2].size = 0x04000000;
dev_priv->mtrr[2].handle =
drm_mtrr_add(dev_priv->mtrr[2].base,
dev_priv->mtrr[2].size, DRM_MTRR_WC);
} else {
DRM_ERROR("strange pci_resource_len %08llx\n",
(unsigned long long)
pci_resource_len(dev->pdev, 0));
}
} else if (dev_priv->chipset != S3_SUPERSAVAGE &&
dev_priv->chipset != S3_SAVAGE2000) {
mmio_base = pci_resource_start(dev->pdev, 0);
fb_rsrc = 1;
fb_base = pci_resource_start(dev->pdev, 1);
fb_size = SAVAGE_FB_SIZE_S4;
aper_rsrc = 1;
aperture_base = fb_base + SAVAGE_APERTURE_OFFSET;
/* this should always be true */
if (pci_resource_len(dev->pdev, 1) == 0x08000000) {
/* Can use one MTRR to cover both fb and
* aperture. */
dev_priv->mtrr[0].base = fb_base;
dev_priv->mtrr[0].size = 0x08000000;
dev_priv->mtrr[0].handle =
drm_mtrr_add(dev_priv->mtrr[0].base,
dev_priv->mtrr[0].size, DRM_MTRR_WC);
} else {
DRM_ERROR("strange pci_resource_len %08llx\n",
(unsigned long long)
pci_resource_len(dev->pdev, 1));
}
} else {
mmio_base = pci_resource_start(dev->pdev, 0);
fb_rsrc = 1;
fb_base = pci_resource_start(dev->pdev, 1);
fb_size = pci_resource_len(dev->pdev, 1);
aper_rsrc = 2;
aperture_base = pci_resource_start(dev->pdev, 2);
/* Automatic MTRR setup will do the right thing. */
}
ret = drm_addmap(dev, mmio_base, SAVAGE_MMIO_SIZE, _DRM_REGISTERS,
_DRM_READ_ONLY, &dev_priv->mmio);
if (ret)
return ret;
ret = drm_addmap(dev, fb_base, fb_size, _DRM_FRAME_BUFFER,
_DRM_WRITE_COMBINING, &dev_priv->fb);
if (ret)
return ret;
ret = drm_addmap(dev, aperture_base, SAVAGE_APERTURE_SIZE,
_DRM_FRAME_BUFFER, _DRM_WRITE_COMBINING,
&dev_priv->aperture);
return ret;
}
int nouveau_load(struct drm_device *dev, unsigned long flags)
{
struct drm_pscnv_virt_private *dev_priv;
resource_size_t mmio_start_offs, call_start_offset;
int ret;
/* allocate the private device data */
dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
if (!dev_priv)
return -ENOMEM;
dev->dev_private = dev_priv;
dev_priv->dev = dev;
dev_priv->flags = flags;
/* resource 0 is mmio regs */
/* resource 1 is hypercall buffer */
/* resource 2 is mapped vram */
/* map the mmio regs */
mmio_start_offs = drm_get_resource_start(dev, 0);
ret = drm_addmap(dev, mmio_start_offs, PSCNV_VIRT_MMIO_SIZE,
_DRM_REGISTERS, _DRM_KERNEL | _DRM_DRIVER, &dev_priv->mmio);
if (ret) {
NV_ERROR(dev, "Unable to initialize the mmio mapping.\n");
return ret;
}
/* map the ring buffer */
call_start_offset = drm_get_resource_start(dev, 1);
ret = drm_addmap(dev, call_start_offset, PSCNV_CALL_AREA_SIZE,
_DRM_REGISTERS, _DRM_KERNEL | _DRM_DRIVER, &dev_priv->call_data);
if (ret) {
NV_ERROR(dev, "Unable to initialize the call data mapping.\n");
return ret;
}
dev_priv->vram_base = drm_get_resource_start(dev, 2);
dev_priv->vram_size = drm_get_resource_len(dev, 2);
/* initialize the hypercall interface */
pscnv_virt_call_init(dev_priv);
ret = drm_irq_install(dev);
if (ret) {
NV_ERROR(dev, "Unable to register the call interrupt.\n");
return ret;
}
memset(dev_priv->vspaces, 0, sizeof(dev_priv->vspaces));
memset(dev_priv->chans, 0, sizeof(dev_priv->chans));
/* the channels are directly mapped to the fourth BAR */
dev_priv->chan_base = drm_get_resource_start(dev, 3);
dev_priv->chan_size = drm_get_resource_len(dev, 3);
dev_priv->is_nv50 = dev_priv->chan_size == 128 * 0x2000 ? 1 : 0;
#if 0
struct drm_nouveau_private *dev_priv;
uint32_t reg0, strap;
resource_size_t mmio_start_offs;
int ret;
dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
if (!dev_priv)
return -ENOMEM;
dev->dev_private = dev_priv;
dev_priv->dev = dev;
dev_priv->flags = flags/* & NOUVEAU_FLAGS*/;
dev_priv->init_state = NOUVEAU_CARD_INIT_DOWN;
NV_DEBUG(dev, "vendor: 0x%X device: 0x%X\n",
dev->pci_vendor, dev->pci_device);
dev_priv->wq = create_workqueue("nouveau");
if (!dev_priv->wq)
return -EINVAL;
/* resource 0 is mmio regs */
/* resource 1 is linear FB */
/* resource 2 is RAMIN (mmio regs + 0x1000000) */
/* resource 6 is bios */
/* map the mmio regs */
mmio_start_offs = drm_get_resource_start(dev, 0);
ret = drm_addmap(dev, mmio_start_offs, 0x00800000, _DRM_REGISTERS,
_DRM_KERNEL | _DRM_DRIVER, &dev_priv->mmio);
if (ret) {
NV_ERROR(dev, "Unable to initialize the mmio mapping. "
"Please report your setup to " DRIVER_EMAIL "\n");
return ret;
}
NV_DEBUG(dev, "regs mapped ok at 0x%llx\n",
(unsigned long long)mmio_start_offs);
#ifdef __BIG_ENDIAN
/* Put the card in BE mode if it's not */
if (nv_rd32(dev, NV03_PMC_BOOT_1))
nv_wr32(dev, NV03_PMC_BOOT_1, 0x00000001);
DRM_MEMORYBARRIER();
#endif
/* Time to determine the card architecture */
reg0 = nv_rd32(dev, NV03_PMC_BOOT_0);
/* We're dealing with >=NV10 */
if ((reg0 & 0x0f000000) > 0) {
/* Bit 27-20 contain the architecture in hex */
dev_priv->chipset = (reg0 & 0xff00000) >> 20;
/* NV04 or NV05 */
} else if ((reg0 & 0xff00fff0) == 0x20004000) {
