static void hns_gmac_set_uc_match(void *mac_drv, u16 en) { struct mac_driver *drv = mac_drv; dsaf_set_dev_bit(drv, GMAC_REC_FILT_CONTROL_REG, GMAC_UC_MATCH_EN_B, !en); dsaf_set_dev_bit(drv, GMAC_STATION_ADDR_HIGH_2_REG, GMAC_ADDR_EN_B, !en); }
static void hns_gmac_disable(void *mac_drv, enum mac_commom_mode mode) { struct mac_driver *drv = (struct mac_driver *)mac_drv; /*disable GE rX/tX */ if ((mode == MAC_COMM_MODE_TX) || (mode == MAC_COMM_MODE_RX_AND_TX)) dsaf_set_dev_bit(drv, GMAC_PORT_EN_REG, GMAC_PORT_TX_EN_B, 0); if ((mode == MAC_COMM_MODE_RX) || (mode == MAC_COMM_MODE_RX_AND_TX)) dsaf_set_dev_bit(drv, GMAC_PORT_EN_REG, GMAC_PORT_RX_EN_B, 0); }
/** *hns_xgmac_set_rx_ignore_pause_frames - set rx pause param about xgmac *@mac_drv: mac driver *@enable:enable rx pause param */ static void hns_xgmac_set_rx_ignore_pause_frames(void *mac_drv, u32 enable) { struct mac_driver *drv = (struct mac_driver *)mac_drv; dsaf_set_dev_bit(drv, XGMAC_MAC_PAUSE_CTRL_REG, XGMAC_PAUSE_CTL_RX_B, !!enable); }
static void hns_gmac_set_duplex_type(void *mac_drv, u8 newval) { struct mac_driver *drv = (struct mac_driver *)mac_drv; dsaf_set_dev_bit(drv, GMAC_DUPLEX_TYPE_REG, GMAC_DUPLEX_TYPE_B, !!newval); }
static void hns_gmac_set_rx_auto_pause_frames(void *mac_drv, u32 newval) { struct mac_driver *drv = (struct mac_driver *)mac_drv; dsaf_set_dev_bit(drv, GMAC_PAUSE_EN_REG, GMAC_PAUSE_EN_RX_FDFC_B, !!newval); }
static void hns_gmac_config_an_mode(void *mac_drv, u8 newval) { struct mac_driver *drv = (struct mac_driver *)mac_drv; dsaf_set_dev_bit(drv, GMAC_TRANSMIT_CONTROL_REG, GMAC_TX_AN_EN_B, !!newval); }
static void hns_gmac_init(void *mac_drv) { u32 port; struct mac_driver *drv = (struct mac_driver *)mac_drv; struct dsaf_device *dsaf_dev = (struct dsaf_device *)dev_get_drvdata(drv->dev); port = drv->mac_id; dsaf_dev->misc_op->ge_srst(dsaf_dev, port, 0); mdelay(10); dsaf_dev->misc_op->ge_srst(dsaf_dev, port, 1); mdelay(10); hns_gmac_disable(mac_drv, MAC_COMM_MODE_RX_AND_TX); hns_gmac_tx_loop_pkt_dis(mac_drv); if (drv->mac_cb->mac_type == HNAE_PORT_DEBUG) hns_gmac_set_uc_match(mac_drv, 0); hns_gmac_config_pad_and_crc(mac_drv, 1); dsaf_set_dev_bit(drv, GMAC_MODE_CHANGE_EN_REG, GMAC_MODE_CHANGE_EB_B, 1); /* reduce gmac tx water line to avoid gmac hang-up * in speed 100M and duplex half. */ dsaf_set_dev_field(drv, GMAC_TX_WATER_LINE_REG, GMAC_TX_WATER_LINE_MASK, GMAC_TX_WATER_LINE_SHIFT, 8); }
static int hns_gmac_adjust_link(void *mac_drv, enum mac_speed speed, u32 full_duplex) { struct mac_driver *drv = (struct mac_driver *)mac_drv; dsaf_set_dev_bit(drv, GMAC_DUPLEX_TYPE_REG, GMAC_DUPLEX_TYPE_B, !!full_duplex); switch (speed) { case MAC_SPEED_10: dsaf_set_dev_field( drv, GMAC_PORT_MODE_REG, GMAC_PORT_MODE_M, GMAC_PORT_MODE_S, 0x6); break; case MAC_SPEED_100: dsaf_set_dev_field( drv, GMAC_PORT_MODE_REG, GMAC_PORT_MODE_M, GMAC_PORT_MODE_S, 0x7); break; case MAC_SPEED_1000: dsaf_set_dev_field( drv, GMAC_PORT_MODE_REG, GMAC_PORT_MODE_M, GMAC_PORT_MODE_S, 0x8); break; default: dev_err(drv->dev, "hns_gmac_adjust_link fail, speed%d mac%d\n", speed, drv->mac_id); return -EINVAL; } return 0; }
/** * hns_ppe_common_init_hw - init ppe common device * @ppe_common: ppe common device * * Return 0 on success, negative on failure */ static int hns_ppe_common_init_hw(struct ppe_common_cb *ppe_common) { enum ppe_qid_mode qid_mode; struct dsaf_device *dsaf_dev = ppe_common->dsaf_dev; enum dsaf_mode dsaf_mode = dsaf_dev->dsaf_mode; dsaf_dev->misc_op->ppe_comm_srst(dsaf_dev, 0); msleep(100); dsaf_dev->misc_op->ppe_comm_srst(dsaf_dev, 1); msleep(100); if (ppe_common->ppe_mode == PPE_COMMON_MODE_SERVICE) { switch (dsaf_mode) { case DSAF_MODE_ENABLE_FIX: case DSAF_MODE_DISABLE_FIX: qid_mode = PPE_QID_MODE0; hns_ppe_set_qid(ppe_common, 0); break; case DSAF_MODE_ENABLE_0VM: case DSAF_MODE_DISABLE_2PORT_64VM: qid_mode = PPE_QID_MODE3; break; case DSAF_MODE_ENABLE_8VM: case DSAF_MODE_DISABLE_2PORT_16VM: qid_mode = PPE_QID_MODE4; break; case DSAF_MODE_ENABLE_16VM: case DSAF_MODE_DISABLE_6PORT_0VM: qid_mode = PPE_QID_MODE5; break; case DSAF_MODE_ENABLE_32VM: case DSAF_MODE_DISABLE_6PORT_16VM: qid_mode = PPE_QID_MODE2; break; case DSAF_MODE_ENABLE_128VM: case DSAF_MODE_DISABLE_6PORT_4VM: qid_mode = PPE_QID_MODE1; break; case DSAF_MODE_DISABLE_2PORT_8VM: qid_mode = PPE_QID_MODE7; break; case DSAF_MODE_DISABLE_6PORT_2VM: qid_mode = PPE_QID_MODE6; break; default: dev_err(ppe_common->dev, "get ppe queue mode failed! dsaf_mode=%d\n", dsaf_mode); return -EINVAL; } hns_ppe_set_qid_mode(ppe_common, qid_mode); } dsaf_set_dev_bit(ppe_common, PPE_COM_COMMON_CNT_CLR_CE_REG, PPE_COMMON_CNT_CLR_CE_B, 1); return 0; }
static int hns_gmac_adjust_link(void *mac_drv, enum mac_speed speed, u32 full_duplex) { u32 tx_ctrl; struct mac_driver *drv = (struct mac_driver *)mac_drv; dsaf_set_dev_bit(drv, GMAC_DUPLEX_TYPE_REG, GMAC_DUPLEX_TYPE_B, !!full_duplex); switch (speed) { case MAC_SPEED_10: dsaf_set_dev_field( drv, GMAC_PORT_MODE_REG, GMAC_PORT_MODE_M, GMAC_PORT_MODE_S, 0x6); break; case MAC_SPEED_100: dsaf_set_dev_field( drv, GMAC_PORT_MODE_REG, GMAC_PORT_MODE_M, GMAC_PORT_MODE_S, 0x7); break; case MAC_SPEED_1000: dsaf_set_dev_field( drv, GMAC_PORT_MODE_REG, GMAC_PORT_MODE_M, GMAC_PORT_MODE_S, 0x8); break; default: dev_err(drv->dev, "hns_gmac_adjust_link fail, speed%d mac%d\n", speed, drv->mac_id); return -EINVAL; } tx_ctrl = dsaf_read_dev(drv, GMAC_TRANSMIT_CONTROL_REG); dsaf_set_bit(tx_ctrl, GMAC_TX_PAD_EN_B, 1); dsaf_set_bit(tx_ctrl, GMAC_TX_CRC_ADD_B, 1); dsaf_write_dev(drv, GMAC_TRANSMIT_CONTROL_REG, tx_ctrl); dsaf_set_dev_bit(drv, GMAC_MODE_CHANGE_EN_REG, GMAC_MODE_CHANGE_EB_B, 1); return 0; }
/** *hns_xgmac_set_tx_auto_pause_frames - set tx pause param about xgmac *@mac_drv: mac driver *@enable:enable tx pause param */ static void hns_xgmac_set_tx_auto_pause_frames(void *mac_drv, u16 enable) { struct mac_driver *drv = (struct mac_driver *)mac_drv; dsaf_set_dev_bit(drv, XGMAC_MAC_PAUSE_CTRL_REG, XGMAC_PAUSE_CTL_TX_B, !!enable); /*if enable is not zero ,set tx pause time */ if (enable) dsaf_write_dev(drv, XGMAC_MAC_PAUSE_TIME_REG, enable); }
static int hns_gmac_config_loopback(void *mac_drv, enum hnae_loop loop_mode, u8 enable) { struct mac_driver *drv = (struct mac_driver *)mac_drv; switch (loop_mode) { case MAC_INTERNALLOOP_MAC: dsaf_set_dev_bit(drv, GMAC_LOOP_REG, GMAC_LP_REG_CF2MI_LP_EN_B, !!enable); break; default: dev_err(drv->dev, "loop_mode error\n"); return -EINVAL; } return 0; }
/** *hns_xgmac_tx_enable - xgmac port tx enable *@drv: mac driver *@value: value of enable */ static void hns_xgmac_tx_enable(struct mac_driver *drv, u32 value) { dsaf_set_dev_bit(drv, XGMAC_MAC_ENABLE_REG, XGMAC_ENABLE_TX_B, !!value); }
void hns_ppe_set_tso_enable(struct hns_ppe_cb *ppe_cb, u32 value) { dsaf_set_dev_bit(ppe_cb, PPEV2_CFG_TSO_EN_REG, 0, !!value); }
static void hns_ppe_cnt_clr_ce(struct hns_ppe_cb *ppe_cb) { dsaf_set_dev_bit(ppe_cb, PPE_TNL_0_5_CNT_CLR_CE_REG, PPE_CNT_CLR_CE_B, 1); }