static int hns_gmac_adjust_link(void *mac_drv, enum mac_speed speed, u32 full_duplex) { struct mac_driver *drv = (struct mac_driver *)mac_drv; dsaf_set_dev_bit(drv, GMAC_DUPLEX_TYPE_REG, GMAC_DUPLEX_TYPE_B, !!full_duplex); switch (speed) { case MAC_SPEED_10: dsaf_set_dev_field( drv, GMAC_PORT_MODE_REG, GMAC_PORT_MODE_M, GMAC_PORT_MODE_S, 0x6); break; case MAC_SPEED_100: dsaf_set_dev_field( drv, GMAC_PORT_MODE_REG, GMAC_PORT_MODE_M, GMAC_PORT_MODE_S, 0x7); break; case MAC_SPEED_1000: dsaf_set_dev_field( drv, GMAC_PORT_MODE_REG, GMAC_PORT_MODE_M, GMAC_PORT_MODE_S, 0x8); break; default: dev_err(drv->dev, "hns_gmac_adjust_link fail, speed%d mac%d\n", speed, drv->mac_id); return -EINVAL; } return 0; }
static void hns_gmac_config_max_frame_length(void *mac_drv, u16 newval) { struct mac_driver *drv = (struct mac_driver *)mac_drv; dsaf_set_dev_field(drv, GMAC_MAX_FRM_SIZE_REG, GMAC_MAX_FRM_SIZE_M, GMAC_MAX_FRM_SIZE_S, newval); dsaf_set_dev_field(drv, GAMC_RX_MAX_FRAME, GMAC_MAX_FRM_SIZE_M, GMAC_MAX_FRM_SIZE_S, newval); }
static void hns_gmac_set_tx_auto_pause_frames(void *mac_drv, u16 newval) { struct mac_driver *drv = (struct mac_driver *)mac_drv; dsaf_set_dev_field(drv, GMAC_FC_TX_TIMER_REG, GMAC_FC_TX_TIMER_M, GMAC_FC_TX_TIMER_S, newval); }
static void hns_ppe_set_qid_mode(struct ppe_common_cb *ppe_common, enum ppe_qid_mode qid_mdoe) { dsaf_set_dev_field(ppe_common, PPE_COM_CFG_QID_MODE_REG, PPE_CFG_QID_MODE_CF_QID_MODE_M, PPE_CFG_QID_MODE_CF_QID_MODE_S, qid_mdoe); }
static void hns_gmac_init(void *mac_drv) { u32 port; struct mac_driver *drv = (struct mac_driver *)mac_drv; struct dsaf_device *dsaf_dev = (struct dsaf_device *)dev_get_drvdata(drv->dev); port = drv->mac_id; dsaf_dev->misc_op->ge_srst(dsaf_dev, port, 0); mdelay(10); dsaf_dev->misc_op->ge_srst(dsaf_dev, port, 1); mdelay(10); hns_gmac_disable(mac_drv, MAC_COMM_MODE_RX_AND_TX); hns_gmac_tx_loop_pkt_dis(mac_drv); if (drv->mac_cb->mac_type == HNAE_PORT_DEBUG) hns_gmac_set_uc_match(mac_drv, 0); hns_gmac_config_pad_and_crc(mac_drv, 1); dsaf_set_dev_bit(drv, GMAC_MODE_CHANGE_EN_REG, GMAC_MODE_CHANGE_EB_B, 1); /* reduce gmac tx water line to avoid gmac hang-up * in speed 100M and duplex half. */ dsaf_set_dev_field(drv, GMAC_TX_WATER_LINE_REG, GMAC_TX_WATER_LINE_MASK, GMAC_TX_WATER_LINE_SHIFT, 8); }
static int hns_gmac_adjust_link(void *mac_drv, enum mac_speed speed, u32 full_duplex) { u32 tx_ctrl; struct mac_driver *drv = (struct mac_driver *)mac_drv; dsaf_set_dev_bit(drv, GMAC_DUPLEX_TYPE_REG, GMAC_DUPLEX_TYPE_B, !!full_duplex); switch (speed) { case MAC_SPEED_10: dsaf_set_dev_field( drv, GMAC_PORT_MODE_REG, GMAC_PORT_MODE_M, GMAC_PORT_MODE_S, 0x6); break; case MAC_SPEED_100: dsaf_set_dev_field( drv, GMAC_PORT_MODE_REG, GMAC_PORT_MODE_M, GMAC_PORT_MODE_S, 0x7); break; case MAC_SPEED_1000: dsaf_set_dev_field( drv, GMAC_PORT_MODE_REG, GMAC_PORT_MODE_M, GMAC_PORT_MODE_S, 0x8); break; default: dev_err(drv->dev, "hns_gmac_adjust_link fail, speed%d mac%d\n", speed, drv->mac_id); return -EINVAL; } tx_ctrl = dsaf_read_dev(drv, GMAC_TRANSMIT_CONTROL_REG); dsaf_set_bit(tx_ctrl, GMAC_TX_PAD_EN_B, 1); dsaf_set_bit(tx_ctrl, GMAC_TX_CRC_ADD_B, 1); dsaf_write_dev(drv, GMAC_TRANSMIT_CONTROL_REG, tx_ctrl); dsaf_set_dev_bit(drv, GMAC_MODE_CHANGE_EN_REG, GMAC_MODE_CHANGE_EB_B, 1); return 0; }
/** * hns_xgmac_tx_lf_rf_insert - insert lf rf control about xgmac * @mac_drv: mac driver * @mode: inserf rf or lf */ static void hns_xgmac_lf_rf_insert(struct mac_driver *mac_drv, u32 mode) { dsaf_set_dev_field(mac_drv, XGMAC_MAC_TX_LF_RF_CONTROL_REG, XGMAC_LF_RF_INSERT_M, XGMAC_LF_RF_INSERT_S, mode); }
/** * hns_ppe_checksum_hw - set ppe checksum caculate * @ppe_device: ppe device * @value: value */ static void hns_ppe_checksum_hw(struct hns_ppe_cb *ppe_cb, u32 value) { dsaf_set_dev_field(ppe_cb, PPE_CFG_PRO_CHECK_EN_REG, 0xfffffff, 0, value); }