static int gf_1_dsi_pll_enable_seq_8916(struct mdss_pll_resources *dsi_pll_res)
{
int pll_locked = 0;
dsi_pll_sw_reset_8916(dsi_pll_res);
/*
* GF PART 1 PLL power up sequence.
* Add necessary delays recommended by hardware.
*/
MDSS_PLL_REG_W(dsi_pll_res->pll_base,
DSI_PHY_PLL_UNIPHY_PLL_CAL_CFG1, 0x14);
MDSS_PLL_REG_W(dsi_pll_res->pll_base,
DSI_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x01);
MDSS_PLL_REG_W(dsi_pll_res->pll_base,
DSI_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x05);
udelay(3);
MDSS_PLL_REG_W(dsi_pll_res->pll_base,
DSI_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x0f);
udelay(500);
dsi_pll_toggle_lock_detect_8916(dsi_pll_res);
pll_locked = dsi_pll_check_lock_status_8916(dsi_pll_res);
return pll_locked ? 0 : -EINVAL;
}
static uint32_t tsmc_dsi_pll_enable_sequence_8916(uint32_t pll_base)
{
uint32_t rc;
dsi_pll_sw_reset_8916(pll_base);
/*
* Add hardware recommended delays between register writes for
* the updates to take effect. These delays are necessary for the
* PLL to successfully lock
*/
writel(0x34, pll_base + 0x0070); /* CAL CFG1*/
writel(0x01, pll_base + 0x0020); /* GLB CFG */
writel(0x05, pll_base + 0x0020); /* GLB CFG */
writel(0x0f, pll_base + 0x0020); /* GLB CFG */
udelay(500);
dsi_pll_toggle_lock_detect_8916(pll_base);
rc = readl(pll_base + 0x00c0) & 0x01;
return rc;
}
