/** * Initialize the DSP emulation */ void DSP_Init(void) { #if ENABLE_DSP_EMU if (bDspEnabled) return; dsp_core_init(DSP_HandleHREQ); dsp56k_init_cpu(); bDspEnabled = true; save_cycles = 0; #endif }
/* Reset */ void dsp_core_reset(void) { int i; LOG_TRACE(TRACE_DSP_STATE, "Dsp: core reset\n"); dsp_core_shutdown(); /* Memory */ memset((void*)dsp_core.periph, 0, sizeof(dsp_core.periph)); memset(dsp_core.stack, 0, sizeof(dsp_core.stack)); memset(dsp_core.registers, 0, sizeof(dsp_core.registers)); dsp_core.dsp_host_rtx = 0; dsp_core.dsp_host_htx = 0; dsp_core.bootstrap_pos = 0; /* Registers */ dsp_core.pc = 0x0000; dsp_core.registers[DSP_REG_OMR]=0x02; for (i=0;i<8;i++) { dsp_core.registers[DSP_REG_M0+i]=0x00ffff; } /* Interruptions */ memset((void*)dsp_core.interrupt_isPending, 0, sizeof(dsp_core.interrupt_isPending)); dsp_core.interrupt_state = DSP_INTERRUPT_NONE; dsp_core.interrupt_instr_fetch = -1; dsp_core.interrupt_save_pc = -1; dsp_core.interrupt_counter = 0; dsp_core.interrupt_pipeline_count = 0; for (i=0;i<5;i++) { dsp_core.interrupt_ipl[i] = 3; } for (i=5;i<12;i++) { dsp_core.interrupt_ipl[i] = -1; } /* host port init, dsp side */ dsp_core.periph[DSP_SPACE_X][DSP_HOST_HSR]=(1<<DSP_HOST_HSR_HTDE); /* host port init, cpu side */ dsp_core.hostport[CPU_HOST_ICR] = 0x0; dsp_core.hostport[CPU_HOST_CVR] = 0x12; dsp_core.hostport[CPU_HOST_ISR] = (1<<CPU_HOST_ISR_TRDY)|(1<<CPU_HOST_ISR_TXDE); dsp_core.hostport[CPU_HOST_IVR] = 0x0f; dsp_core.hostport[CPU_HOST_RX0] = 0x0; /* SSI registers */ dsp_core.periph[DSP_SPACE_X][DSP_SSI_SR]=1<<DSP_SSI_SR_TDE; dsp_core.ssi.waitFrameTX = 1; dsp_core.ssi.waitFrameRX = 1; dsp_core.ssi.TX = 0; dsp_core.ssi.RX = 0; dsp_core.ssi.dspPlay_handshakeMode_frame = 0; dsp_core_ssi_configure(DSP_SSI_CRA, 0); dsp_core_ssi_configure(DSP_SSI_CRB, 0); /* Other hardware registers */ dsp_core.periph[DSP_SPACE_X][DSP_IPR]=0; dsp_core.periph[DSP_SPACE_X][DSP_BCR]=0xffff; /* Misc */ dsp_core.loop_rep = 0; LOG_TRACE(TRACE_DSP_STATE, "Dsp: reset done\n"); dsp56k_init_cpu(); }