/*
* OMAP4 does not allow aggressive DSS clock cutting, so we must keep the
* clocks enabled during display use. These next two methods on OMAP4
* enable and disable all DSS clocks (main and needed optional).
*/
int dss_mainclk_enable()
{
int ret = 0;
DSSDBG_PCP_PRINT("%s: display_debug PCP in dss_mainclk_enable\n", __func__);
if (!dss.mainclk_state) {
if (cpu_is_omap44xx() || cpu_is_omap34xx())
ret = dss_opt_clock_enable();
if (ret)
dss_opt_clock_disable();
#ifdef CONFIG_PM_RUNTIME
else
ret = pm_runtime_get_sync(&dss.pdev->dev);
#endif
if (!ret) {
dss.mainclk_state = true;
DSSDBG_PCP_PRINT("%s: display_debug PCP making dss.mainclk_state = true, ret %d\n", __func__, ret);
}
} else {
DSSDBG_PCP_PRINT("%s: display_debug PCP dss_opt_clock_enable failed , returning -EBUSY\n", __func__);
return -EBUSY;
}
return ret;
}
/*
* OMAP4 does not allow aggressive DSS clock cutting, so we must keep the
* clocks enabled during display use. These next two methods on OMAP4
* enable and disable all DSS clocks (main and needed optional).
*/
int dss_mainclk_enable()
{
int ret = 0;
if (!dss.mainclk_state) {
if (cpu_is_omap44xx() || cpu_is_omap34xx())
ret = dss_opt_clock_enable();
printk("[JamesLee] dss_opt_clock_enable() = %d\n", ret);
if (!ret)
{
ret = pm_runtime_get_sync(&dss.pdev->dev);
printk("[JamesLee] pm_runtime_get_sync() = %d\n", ret);
}
else
dss_opt_clock_disable();
#if 0
if (!ret)
dss.mainclk_state = true;
#else /* JamesLee_OCT26 */
if (ret>=0)
dss.mainclk_state = true;
#endif
} else {
return -EBUSY;
}
return ret;
}
/*
* OMAP4 does not allow aggressive DSS clock cutting, so we must keep the
* clocks enabled during display use. These next two methods on OMAP4
* enable and disable all DSS clocks (main and needed optional).
*/
int dss_mainclk_enable()
{
int ret = 0;
if (!dss.mainclk_state) {
if (cpu_is_omap44xx() || cpu_is_omap34xx())
ret = dss_opt_clock_enable();
if (ret)
dss_opt_clock_disable();
#ifdef CONFIG_PM_RUNTIME
else {
ret = pm_runtime_get_sync(&dss.pdev->dev);
/* Work around added by Shankar
* some time pm_runtime_get_sync fails to enable DSS clock
*/
{
#define CM_DSS_DSS_CLKCTRL 0x4A009120
int val =0;
val = omap_readl(CM_DSS_DSS_CLKCTRL);
if (((val & 0x02) != 0x02) && ret == 0 ){
val = val | (1<<1);
omap_writel(val, CM_DSS_DSS_CLKCTRL);
printk("%s[%d] pm_runtime_get_sync failed set DSS clk reg, setting it forcefully clk=0x%x \n",
__func__, __LINE__, omap_readl(CM_DSS_DSS_CLKCTRL));
}
}
}
#endif
if (!ret)
dss.mainclk_state = true;
} else {
return -EBUSY;
}
return ret;
}
/*
* OMAP4 does not allow aggressive DSS clock cutting, so we must keep the
* clocks enabled during display use. These next two methods on OMAP4
* enable and disable all DSS clocks (main and needed optional).
*/
int dss_mainclk_enable()
{
int ret = 0;
if (!dss.mainclk_state) {
if (cpu_is_omap44xx() || cpu_is_omap34xx())
ret = dss_opt_clock_enable();
if (ret)
dss_opt_clock_disable();
#ifdef CONFIG_PM_RUNTIME
else
ret = pm_runtime_get_sync(&dss.pdev->dev);
#endif
if (!ret)
dss.mainclk_state = true;
} else {
return -EBUSY;
}
return ret;
}