/* TODO: Parse UART config from the command line */
static int __init exynos4210_uart_init(struct dt_device_node *dev,
const void *data)
{
const char *config = data;
struct exynos4210_uart *uart;
int res;
u64 addr, size;
if ( strcmp(config, "") )
{
early_printk("WARNING: UART configuration is not supported\n");
}
uart = &exynos4210_com;
/* uart->clock_hz = 0x16e3600; */
uart->baud = BAUD_AUTO;
uart->data_bits = 8;
uart->parity = PARITY_NONE;
uart->stop_bits = 1;
res = dt_device_get_address(dev, 0, &addr, &size);
if ( res )
{
early_printk("exynos4210: Unable to retrieve the base"
" address of the UART\n");
return res;
}
uart->regs = ioremap_nocache(addr, size);
if ( !uart->regs )
{
early_printk("exynos4210: Unable to map the UART memory\n");
return -ENOMEM;
}
res = dt_device_get_irq(dev, 0, &uart->irq);
if ( res )
{
early_printk("exynos4210: Unable to retrieve the IRQ\n");
return res;
}
uart->vuart.base_addr = addr;
uart->vuart.size = size;
uart->vuart.data_off = UTXH;
uart->vuart.status_off = UTRSTAT;
uart->vuart.status = UTRSTAT_TXE | UTRSTAT_TXFE;
/* Register with generic serial driver. */
serial_register_uart(SERHND_DTUART, &exynos4210_uart_driver, uart);
dt_device_set_used_by(dev, DOMID_XEN);
return 0;
}
/* Set up the timer on the boot CPU */
int __init init_xen_time(void)
{
static const struct dt_device_match timer_ids[] __initconst =
{
DT_MATCH_TIMER,
{ /* sentinel */ },
};
struct dt_device_node *dev;
int res;
unsigned int i;
u32 rate;
dev = dt_find_matching_node(NULL, timer_ids);
if ( !dev )
panic("Unable to find a compatible timer in the device tree");
dt_device_set_used_by(dev, DOMID_XEN);
/* Retrieve all IRQs for the timer */
for ( i = TIMER_PHYS_SECURE_PPI; i < MAX_TIMER_PPI; i++ )
{
res = dt_device_get_irq(dev, i, &timer_irq[i]);
if ( res )
panic("Timer: Unable to retrieve IRQ %u from the device tree", i);
}
printk("Generic Timer IRQ: phys=%u hyp=%u virt=%u\n",
timer_irq[TIMER_PHYS_NONSECURE_PPI].irq,
timer_irq[TIMER_HYP_PPI].irq,
timer_irq[TIMER_VIRT_PPI].irq);
res = platform_init_time();
if ( res )
panic("Timer: Cannot initialize platform timer");
/* Check that this CPU supports the Generic Timer interface */
if ( !cpu_has_gentimer )
panic("CPU does not support the Generic Timer v1 interface");
res = dt_property_read_u32(dev, "clock-frequency", &rate);
if ( res )
cpu_khz = rate / 1000;
else
cpu_khz = READ_SYSREG32(CNTFRQ_EL0) / 1000;
boot_count = READ_SYSREG64(CNTPCT_EL0);
printk("Using generic timer at %lu KHz\n", cpu_khz);
return 0;
}
static int __init omap_uart_init(struct dt_device_node *dev,
const void *data)
{
const char *config = data;
struct omap_uart *uart;
u32 clkspec;
int res;
u64 addr, size;
if ( strcmp(config, "") )
printk("WARNING: UART configuration is not supported\n");
uart = &omap_com;
res = dt_property_read_u32(dev, "clock-frequency", &clkspec);
if ( !res )
{
printk("omap-uart: Unable to retrieve the clock frequency\n");
return -EINVAL;
}
uart->clock_hz = clkspec;
uart->baud = 115200;
uart->data_bits = 8;
uart->parity = UART_PARITY_NONE;
uart->stop_bits = 1;
res = dt_device_get_address(dev, 0, &addr, &size);
if ( res )
{
printk("omap-uart: Unable to retrieve the base"
" address of the UART\n");
return res;
}
res = dt_device_get_irq(dev, 0, &uart->irq);
if ( res )
{
printk("omap-uart: Unable to retrieve the IRQ\n");
return res;
}
uart->regs = ioremap_nocache(addr, size);
if ( !uart->regs )
{
printk("omap-uart: Unable to map the UART memory\n");
return -ENOMEM;
}
uart->vuart.base_addr = addr;
uart->vuart.size = size;
uart->vuart.data_off = UART_THR;
uart->vuart.status_off = UART_LSR << REG_SHIFT;
uart->vuart.status = UART_LSR_THRE;
/* Register with generic serial driver */
serial_register_uart(SERHND_DTUART, &omap_uart_driver, uart);
dt_device_set_used_by(dev, DOMID_XEN);
return 0;
}
