int skge_dump_regs(struct ethtool_drvinfo *info, struct ethtool_regs *regs)
{
const u32 *r = (const u32 *) regs->data;
int dual = !(regs->data[0x11a] & 1);
dump_pci(regs->data + 0x380);
dump_control(regs->data);
printf("\nBus Management Unit\n");
printf("-------------------\n");
printf("CSR Receive Queue 1 0x%08X\n", r[24]);
printf("CSR Sync Queue 1 0x%08X\n", r[26]);
printf("CSR Async Queue 1 0x%08X\n", r[27]);
if (dual) {
printf("CSR Receive Queue 2 0x%08X\n", r[25]);
printf("CSR Async Queue 2 0x%08X\n", r[29]);
printf("CSR Sync Queue 2 0x%08X\n", r[28]);
}
dump_mac(regs->data);
dump_gmac("GMAC 1", regs->data + 0x2800);
dump_timer("Timer", regs->data + 0x130);
dump_timer("Blink Source", regs->data +0x170);
dump_queue("Receive Queue 1", regs->data +0x400, 1);
dump_queue("Sync Transmit Queue 1", regs->data +0x600, 0);
dump_queue("Async Transmit Queue 1", regs->data +0x680, 0);
dump_ram("Receive RAMbuffer 1", regs->data+0x800);
dump_ram("Sync Transmit RAMbuffer 1", regs->data+0xa00);
dump_ram("Async Transmit RAMbuffer 1", regs->data+0xa80);
dump_fifo("Receive MAC FIFO 1", regs->data+0xc00);
dump_fifo("Transmit MAC FIFO 1", regs->data+0xd00);
if (dual) {
dump_gmac("GMAC 1", regs->data + 0x2800);
dump_queue("Receive Queue 2", regs->data +0x480, 1);
dump_queue("Async Transmit Queue 2", regs->data +0x780, 0);
dump_queue("Sync Transmit Queue 2", regs->data +0x700, 0);
dump_ram("Receive RAMbuffer 2", regs->data+0x880);
dump_ram("Sync Transmit RAMbuffer 2", regs->data+0xb00);
dump_ram("Async Transmit RAMbuffer 21", regs->data+0xb80);
dump_fifo("Receive MAC FIFO 2", regs->data+0xc80);
dump_fifo("Transmit MAC FIFO 2", regs->data+0xd80);
}
dump_timer("Descriptor Poll", regs->data+0xe00);
return 0;
}
int do_fifo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
int i;
int n = 0;
u32 ctrl, data, f;
char str[] = "\\|/-";
int abort = 0;
int count = 0;
int count2 = 0;
switch (argc) {
case 1:
/* print all fifos status information */
printf("fifo level status\n");
printf("______________________________\n");
for (i=0; i<FIFO_COUNT; i++) {
ctrl = FPGA_IN32(&fpga->fifo[i].ctrl);
printf(" %d %3d %s%s%s %s\n",
i, ctrl & (FIFO_LEVEL_MASK | FIFO_FULL),
ctrl & FIFO_FULL ? "FULL " : "",
ctrl & FIFO_EMPTY ? "EMPTY " : "",
ctrl & (FIFO_FULL|FIFO_EMPTY) ? "" : "NOT EMPTY",
ctrl & FIFO_OVERFLOW ? "OVERFLOW" : "");
}
break;
case 2:
/* completely read out fifo 'n' */
if (!strcmp(argv[1],"read")) {
printf(" # fifo level data\n");
printf("______________________________\n");
for (i=0; i<FIFO_COUNT; i++)
dump_fifo(fpga, i, &n);
} else if (!strcmp(argv[1],"wait")) {
got_fifoirq = 0;
irq_install_handler(IRQ0_FPGA,
(interrupt_handler_t *)fpga_interrupt,
fpga);
printf(" # fifo level data\n");
printf("______________________________\n");
/* enable all fifo interrupts */
FPGA_OUT32(&fpga->hostctrl,
HOSTCTRL_FIFOIE_GATE | HOSTCTRL_FIFOIE_FLAG);
for (i=0; i<FIFO_COUNT; i++) {
/* enable interrupts from all fifos */
FPGA_SETBITS(&fpga->fifo[i].ctrl, FIFO_IE);
}
while (1) {
/* wait loop */
while (!got_fifoirq) {
count++;
if (!(count % 100)) {
count2++;
putc(0x08); /* backspace */
putc(str[count2 % 4]);
}
/* Abort if ctrl-c was pressed */
if ((abort = ctrlc())) {
puts("\nAbort\n");
break;
}
udelay(1000);
}
if (abort)
break;
/* simple fifo backend */
if (got_fifoirq) {
for (i=0; i<FIFO_COUNT; i++)
dump_fifo(fpga, i, &n);
got_fifoirq = 0;
/* unmask global fifo irq */
FPGA_OUT32(&fpga->hostctrl,
HOSTCTRL_FIFOIE_GATE |
HOSTCTRL_FIFOIE_FLAG);
}
}
/* disable all fifo interrupts */
FPGA_OUT32(&fpga->hostctrl, HOSTCTRL_FIFOIE_GATE);
for (i=0; i<FIFO_COUNT; i++)
FPGA_CLRBITS(&fpga->fifo[i].ctrl, FIFO_IE);
irq_free_handler(IRQ0_FPGA);
} else {
printf("Usage:\nfifo %s\n", cmdtp->help);
return 1;
}
break;
case 4:
case 5:
if (!strcmp(argv[1],"write")) {
/* get fifo number or fifo address */
f = simple_strtoul(argv[2], NULL, 16);
/* data paramter */
data = simple_strtoul(argv[3], NULL, 16);
/* get optional count parameter */
n = 1;
if (argc >= 5)
n = (int)simple_strtoul(argv[4], NULL, 10);
if (f < FIFO_COUNT) {
printf("writing %d x %08x to fifo %d\n",
n, data, f);
for (i=0; i<n; i++)
FPGA_OUT32(&fpga->fifo[f].data, data);
} else {
printf("writing %d x %08x to fifo port at "
"address %08x\n",
n, data, f);
for (i=0; i<n; i++)
out_be32((void *)f, data);
}
} else {
printf("Usage:\nfifo %s\n", cmdtp->help);
return 1;
}
break;
default:
printf("Usage:\nfifo %s\n", cmdtp->help);
return 1;
}
return 0;
}
