static void bochs_init_linear_fb(struct device *dev)
{
struct edid edid;
int id, mem, bar;
u32 addr;
/* bochs dispi detection */
id = bochs_read(VBE_DISPI_INDEX_ID);
if ((id & 0xfff0) != VBE_DISPI_ID0) {
printk(BIOS_DEBUG, "QEMU VGA: bochs dispi: ID mismatch.\n");
return;
}
mem = bochs_read(VBE_DISPI_INDEX_VIDEO_MEMORY_64K) * 64 * 1024;
/* find lfb pci bar */
addr = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
if ((addr & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_MEMORY) {
/* qemu -vga {std,qxl} */
bar = 0;
} else {
/* qemu -vga vmware */
addr = pci_read_config32(dev, PCI_BASE_ADDRESS_1);
bar = 1;
}
addr &= ~PCI_BASE_ADDRESS_MEM_ATTR_MASK;
if (!addr)
return;
printk(BIOS_DEBUG, "QEMU VGA: bochs dispi interface found, "
"%d MiB video memory\n", mem / (1024 * 1024));
printk(BIOS_DEBUG, "QEMU VGA: framebuffer @ %x (pci bar %d)\n",
addr, bar);
/* setup video mode */
bochs_write(VBE_DISPI_INDEX_ENABLE, 0);
bochs_write(VBE_DISPI_INDEX_BANK, 0);
bochs_write(VBE_DISPI_INDEX_BPP, 32);
bochs_write(VBE_DISPI_INDEX_XRES, width);
bochs_write(VBE_DISPI_INDEX_YRES, height);
bochs_write(VBE_DISPI_INDEX_VIRT_WIDTH, width);
bochs_write(VBE_DISPI_INDEX_VIRT_HEIGHT, height);
bochs_write(VBE_DISPI_INDEX_X_OFFSET, 0);
bochs_write(VBE_DISPI_INDEX_Y_OFFSET, 0);
bochs_write(VBE_DISPI_INDEX_ENABLE,
VBE_DISPI_ENABLED | VBE_DISPI_LFB_ENABLED);
outb(0x20, 0x3c0); /* disable blanking */
/* setup coreboot framebuffer */
edid.mode.ha = width;
edid.mode.va = height;
edid.panel_bits_per_color = 8;
edid.panel_bits_per_pixel = 24;
edid_set_framebuffer_bits_per_pixel(&edid, 32, 0);
set_vbe_mode_info_valid(&edid, addr);
}
void rk_display_init(device_t dev, u32 lcdbase,
unsigned long fb_size)
{
struct edid edid;
struct soc_rockchip_rk3288_config *conf = dev->chip_info;
uint32_t lower = ALIGN_DOWN(lcdbase, MiB);
uint32_t upper = ALIGN_UP(lcdbase + fb_size, MiB);
enum vop_modes detected_mode = VOP_MODE_UNKNOWN;
printk(BIOS_SPEW, "LCD framebuffer @%p\n", (void *)(lcdbase));
memset((void *)lcdbase, 0, fb_size); /* clear the framebuffer */
dcache_clean_invalidate_by_mva((void *)lower, upper - lower);
mmu_config_range(lower / MiB, (upper - lower) / MiB, DCACHE_OFF);
switch (conf->vop_mode) {
case VOP_MODE_NONE:
return;
case VOP_MODE_AUTO_DETECT:
/* try EDP first, then HDMI */
case VOP_MODE_EDP:
printk(BIOS_DEBUG, "Attempting to setup EDP display.\n");
rkclk_configure_edp();
rkclk_configure_vop_aclk(conf->vop_id, 192 * MHz);
rk_edp_init(conf->vop_id);
if (rk_edp_get_edid(&edid) == 0) {
detected_mode = VOP_MODE_EDP;
break;
} else {
printk(BIOS_WARNING, "Cannot get EDID from EDP.\n");
if (conf->vop_mode == VOP_MODE_EDP)
return;
}
/* fall thru */
case VOP_MODE_HDMI:
printk(BIOS_DEBUG, "Attempting to setup HDMI display.\n");
rkclk_configure_hdmi();
rkclk_configure_vop_aclk(conf->vop_id, 384 * MHz);
rk_hdmi_init(conf->vop_id);
if (rk_hdmi_get_edid(&edid) == 0) {
detected_mode = VOP_MODE_HDMI;
break;
} else {
printk(BIOS_WARNING, "Cannot get EDID from HDMI.\n");
if (conf->vop_mode == VOP_MODE_HDMI)
return;
}
/* fall thru */
default:
printk(BIOS_WARNING, "Cannot read any edid info, aborting.\n");
return;
}
if (rkclk_configure_vop_dclk(conf->vop_id, edid.mode.pixel_clock * KHz)) {
printk(BIOS_WARNING, "config vop err\n");
return;
}
edid_set_framebuffer_bits_per_pixel(&edid,
conf->framebuffer_bits_per_pixel);
rkvop_mode_set(conf->vop_id, &edid, detected_mode);
rkvop_enable(conf->vop_id, lcdbase, &edid);
switch (detected_mode) {
case VOP_MODE_HDMI:
if (rk_hdmi_enable(&edid)) {
printk(BIOS_WARNING, "hdmi enable err\n");
return;
}
/*
* HACK: if we do remove this delay, HDMI TV may not show
* anythings. So we make an delay here, ensure TV have
* enough time to respond.
*/
mdelay(2000);
break;
case VOP_MODE_EDP:
default:
if (rk_edp_enable()) {
printk(BIOS_WARNING, "edp enable err\n");
return;
}
mainboard_power_on_backlight();
break;
}
set_vbe_mode_info_valid(&edid, (uintptr_t)lcdbase);
}
/* this is really aimed at the lcd panel. That said, there are two display
* devices on this part and we may someday want to extend it for other boards.
*/
void display_startup(device_t dev)
{
struct soc_nvidia_tegra124_config *config = dev->chip_info;
struct display_controller *disp_ctrl = (void *)config->display_controller;
struct pwm_controller *pwm = (void *)TEGRA_PWM_BASE;
struct tegra_dc *dc = &dc_data;
u32 plld_rate;
/* init dc */
dc->base = (void *)TEGRA_ARM_DISPLAYA;
dc->config = config;
config->dc_data = dc;
/* Note dp_init may read EDID and change some config values. */
dp_init(config);
/* should probably just make it all MiB ... in future */
u32 framebuffer_size_mb = config->framebuffer_size / MiB;
u32 framebuffer_base_mb= config->framebuffer_base / MiB;
/* light it all up */
/* This one may have been done in romstage but that's ok for now. */
if (config->panel_vdd_gpio){
gpio_output(config->panel_vdd_gpio, 1);
printk(BIOS_SPEW,"%s: panel_vdd setting gpio %08x to %d\n",
__func__, config->panel_vdd_gpio, 1);
}
udelay(config->vdd_delay_ms * 1000);
if (config->backlight_vdd_gpio){
gpio_output(config->backlight_vdd_gpio, 1);
printk(BIOS_SPEW,"%s: backlight vdd setting gpio %08x to %d\n",
__func__, config->backlight_vdd_gpio, 1);
}
if (config->lvds_shutdown_gpio){
gpio_output(config->lvds_shutdown_gpio, 0);
printk(BIOS_SPEW,"%s: lvds shutdown setting gpio %08x to %d\n",
__func__, config->lvds_shutdown_gpio, 0);
}
if (framebuffer_size_mb == 0){
framebuffer_size_mb = ALIGN_UP(config->xres * config->yres *
(config->framebuffer_bits_per_pixel / 8), MiB)/MiB;
}
if (! framebuffer_base_mb)
framebuffer_base_mb = fb_base_mb();
config->framebuffer_size = framebuffer_size_mb * MiB;
config->framebuffer_base = framebuffer_base_mb * MiB;
mmu_config_range(framebuffer_base_mb, framebuffer_size_mb,
DCACHE_WRITETHROUGH);
printk(BIOS_SPEW, "LCD frame buffer at %dMiB to %dMiB\n", framebuffer_base_mb,
framebuffer_base_mb + framebuffer_size_mb);
/* GPIO magic here if needed to start powering up things. You
* really only want to enable vdd, wait a bit, and then enable
* the panel. However ... the timings in the tegra20 dts make
* no sense to me. I'm pretty sure they're wrong.
* The panel_vdd is done in the romstage, so we need only
* light things up here once we're sure it's all working.
*/
/* The plld is programmed with the assumption of the SHIFT_CLK_DIVIDER
* and PIXEL_CLK_DIVIDER are zero (divide by 1). See the
* update_display_mode() for detail.
*/
plld_rate = clock_display(config->pixel_clock * 2);
if (plld_rate == 0) {
printk(BIOS_ERR, "dc: clock init failed\n");
return;
} else if (plld_rate != config->pixel_clock * 2) {
printk(BIOS_WARNING, "dc: plld rounded to %u\n", plld_rate);
config->pixel_clock = plld_rate / 2;
}
/* Init dc */
if (tegra_dc_init(disp_ctrl)) {
printk(BIOS_ERR, "dc: init failed\n");
return;
}
/* Configure dc mode */
if (update_display_mode(disp_ctrl, config)) {
printk(BIOS_ERR, "dc: failed to configure display mode.\n");
return;
}
/* Enable dp */
dp_enable(dc->out);
/* Init frame buffer */
memset((void *)(framebuffer_base_mb*MiB), 0x00,
framebuffer_size_mb*MiB);
update_window(disp_ctrl, config);
/* Set up Tegra PWM n (where n is specified in config->pwm) to drive the
* panel backlight.
*/
printk(BIOS_SPEW, "%s: enable panel backlight pwm\n", __func__);
WRITEL(((1 << NV_PWM_CSR_ENABLE_SHIFT) |
(220 << NV_PWM_CSR_PULSE_WIDTH_SHIFT) | /* 220/256 */
0x02e), /* frequency divider */
&pwm->pwm[config->pwm].csr);
udelay(config->pwm_to_bl_delay_ms * 1000);
if (config->backlight_en_gpio){
gpio_output(config->backlight_en_gpio, 1);
printk(BIOS_SPEW,"%s: backlight enable setting gpio %08x to %d\n",
__func__, config->backlight_en_gpio, 1);
}
printk(BIOS_INFO, "%s: display init done.\n", __func__);
/* tell depthcharge ...
*/
struct edid edid;
edid.mode.va = config->yres;
edid.mode.ha = config->xres;
edid_set_framebuffer_bits_per_pixel(&edid,
config->framebuffer_bits_per_pixel, 32);
set_vbe_mode_info_valid(&edid, (uintptr_t)(framebuffer_base_mb*MiB));
}
