int platform_init(struct sof *sof)
{
int ret;
struct dai *esai;
clock_init();
scheduler_init();
platform_timer_start(platform_timer);
sa_init(sof);
clock_set_freq(CLK_CPU(cpu_get_id()), CLK_MAX_CPU_HZ);
/* init DMA */
ret = edma_init();
if (ret < 0)
return -ENODEV;
/* initialize the host IPC mechanims */
ipc_init(sof);
ret = dai_init();
if (ret < 0)
return -ENODEV;
esai = dai_get(SOF_DAI_IMX_ESAI, 0, DAI_CREAT);
if (!esai)
return -ENODEV;
dai_probe(esai);
return 0;
}
void initActors(){
edma_init();
tw_gen(gen_twi16k, 16*1024);
tw_gen(gen_twi8k, 8*1024);
tw_gen(gen_twi4k, 4*1024);
tw_gen(gen_twi2k, 2*1024);
tw_gen(gen_twi1k, 1024);
for(int i=0; i<32*1024; i++){
twi64k[i].real = -sin(-2*M_PI*i/(64*1024));
twi64k[i].imag = cos(-2*M_PI*i/(64*1024));
}
}
static int edma_transfer_inner(edma_conf_t* edma_conf) {
#define RETRY_COUNT 200
edma_stat_t dma_stat[1];
int i;
edma_init(DMA_NR, edma_conf);
edma_param(DMA_NR, edma_conf);
edma_interrupt(DMA_NR, edma_conf);
#if 0
dump_regs_word("param0", (uint32_t)&DMA_NR->CC.PAEntry[pa_conf[0].index], sizeof(PaRAM_entry_t));
if (edma_conf->pa_cnt > 1) {
dump_regs_word("param1", (uint32_t)&DMA_NR->CC.PAEntry[pa_conf[1].index], sizeof(PaRAM_entry_t));
}
#endif
edma_transfer(DMA_NR, edma_conf);
if (AM18X_OK == edma_status(DMA_NR, dma_stat)) {
for (i = 0; dma_stat->status[i] != NULL; i++) {
printk("S%d %s\n", i, dma_stat->status[i]);
}
printk("completed requests # = %d\n", dma_stat->comp_actv);
printk("queue0 events # = %d\n", dma_stat->queue_evts[0]);
printk("queue1 events # = %d\n", dma_stat->queue_evts[1]);
}
for (i = 0; i < RETRY_COUNT && AM18X_OK != edma_completed(DMA_NR, edma_conf); i++) {
printk(".");
}
if (i != 0) {
printk("\n");
}
#if 0
dump_regs_word("Region0", (uint32_t)&DMA_NR->CC.Region0, sizeof(EDMA3CC_rgn_t));
dump_regs_word("param0", (uint32_t)&DMA_NR->CC.PAEntry[pa_conf[0].index], sizeof(PaRAM_entry_t));
if (edma_conf->pa_cnt > 1) {
dump_regs_word("param1", (uint32_t)&DMA_NR->CC.PAEntry[pa_conf[1].index], sizeof(PaRAM_entry_t));
}
#endif
if (i >= RETRY_COUNT) {
return -1;
}
return 0;
}
int main (void)
{
uint8_t msg;
uint32_t timeout = 0;
uint32_t var;
volatile uint16_t count;
OSA_Init();
hardware_init();
dbg_uart_init();
configure_spi_pins(HW_SPI0);
printf("dspi_edma_test_slave\r\n");
printf("\r\nDemo started...\r\n");
// Initialize configuration
edma_init();
edma_dspi_rx_setup(kEDMAChannel2, (uint32_t)&g_slaveRxBuffer);
dspi_slave_setup(HW_SPI0, SPI_BAUDRATE);
printf("Press space bar to begin.\r\n");
msg = 'A';
while(msg != ' ')
{
msg = getchar();
}
printf("\r\nDemo started...\r\n");
// Slave only have PCS0
PORT_HAL_SetMuxMode(PORTC_BASE, 0u, kPortMuxAlt7);
// Enable eDMA channels requests to initiate DSPI transfers.
EDMA_HAL_SetDmaRequestCmd(DMA_BASE, kEDMAChannel2, true);
DSPI_HAL_StartTransfer(SPI0_BASE);
// Waiting transfer complete
printf("waiting transfer complete...\r\n");
while((bReceivedFlag == false) & (timeout < 50))
{
OSA_TimeDelay(100);
timeout++;
}
if(bReceivedFlag == false)
{
printf("No date received, please check connections\r\n");
}
printf("received data:\r\n");
for(count = 0; count < TEST_DATA_LEN; count++)
{
var = g_slaveRxBuffer[count];
printf("%08X\t", (unsigned int)var);
if((count + 1) % 4 == 0)
{
printf("\r\n");
}
}
printf("\r\nEnd of demo.\r\n");
}
