static int ehci_arc_resume(struct platform_device *pdev)
{
struct usb_hcd *hcd = platform_get_drvdata(pdev);
struct ehci_hcd *ehci = hcd_to_ehci(hcd);
u32 tmp;
struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
dbg("%s pdev=0x%p pdata=0x%p ehci=0x%p hcd=0x%p\n",
__FUNCTION__, pdev, pdata, ehci, hcd);
vdbg("%s ehci->regs=0x%p hcd->regs=0x%p usbmode=0x%x\n",
__FUNCTION__, ehci->regs, hcd->regs, pdata->usbmode);
tmp = USBMODE_CM_HOST;
if (ehci_big_endian_mmio(ehci))
tmp |= USBMODE_BE;
ehci_writel(ehci, tmp, (u32 *)pdata->usbmode);
memcpy(ehci->regs, (void *)&usb_ehci_regs, sizeof(struct ehci_regs));
set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
hcd->state = HC_STATE_RUNNING;
pdev->dev.power.power_state = PMSG_ON;
tmp = ehci_readl(ehci, &ehci->regs->command);
tmp |= CMD_RUN;
ehci_writel(ehci, tmp, &ehci->regs->command);
fsl_platform_set_vbus_power(pdata, 1);
usb_hcd_resume_root_hub(hcd);
return 0;
}
/* put TDI/ARC silicon into EHCI mode */
static void tdi_reset (struct ehci_hcd *ehci)
{
u32 __iomem *reg_ptr;
u32 tmp;
reg_ptr = (u32 __iomem *)(((u8 __iomem *)ehci->regs) + USBMODE);
tmp = ehci_readl(ehci, reg_ptr);
tmp |= USBMODE_CM_HC;
/* The default byte access to MMR space is LE after
* controller reset. Set the required endian mode
* for transfer buffers to match the host microprocessor
*/
if (ehci_big_endian_mmio(ehci))
tmp |= USBMODE_BE;
ehci_writel(ehci, tmp, reg_ptr);
}